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Add local HLS dev setup: clangd, pragma highlighting + linting, local C-sim

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This commit is contained in:
Movitz Aaron
2026-10-24 17:13:18 +01:00
parent e036c194ed
commit 04b7425598
180 changed files with 745644 additions and 0 deletions
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Practicals/practical-3b/game_of_life_practical3b/.clangd Normal file
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# Tell clangd to ignore the Vitis-generated compile_commands.json (its paths
# point at /home/userfs/... on the remote server and its flags are Xilinx-only)
# and use the local flag set in Practicals/hlsdev/clangd instead.
CompileFlags:
CompilationDatabase: ../../hlsdev/clangd

21
Practicals/practical-3b/game_of_life_practical3b/.gitignore vendored Normal file
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# Ignore build output directory
/build
/export
# Ignore object files and dependent files
.o
.d
#Ignore logs folder and log files
/logs
.log
#Ignore lock files
.lock
.bin
.pdi
.vitisWorkspace.json
_ide/logs
_ide/.wsdata

27
Practicals/practical-3b/game_of_life_practical3b/compile_commands.json Normal file
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@@ -0,0 +1,27 @@
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],
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],
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}
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246
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; ModuleID = '/home/userfs/b/brs544/vitis_workspace/game_of_life_practical3b/game_of_life_practical3b/hls/.autopilot/db/a.g.ld.5.gdce.bc'
source_filename = "llvm-link"
target datalayout = "e-m:e-i64:64-i128:128-i256:256-i512:512-i1024:1024-i2048:2048-i4096:4096-n8:16:32:64-S128-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024"
target triple = "fpga64-xilinx-none"
; Function Attrs: inaccessiblemem_or_argmemonly noinline willreturn
define void @apatb_game_of_life_step_ir(i32* noalias nocapture nonnull readonly "fpga.decayed.dim.hint"="4" "partition" %in_words, i32* noalias nocapture nonnull "fpga.decayed.dim.hint"="4" "partition" %out_words) local_unnamed_addr #0 {
entry:
%0 = bitcast i32* %in_words to [4 x i32]*
%in_words_copy_0 = alloca i32, align 512
%in_words_copy_1 = alloca i32, align 512
%in_words_copy_2 = alloca i32, align 512
%in_words_copy_3 = alloca i32, align 512
%1 = bitcast i32* %out_words to [4 x i32]*
%out_words_copy_0 = alloca i32, align 512
%out_words_copy_1 = alloca i32, align 512
%out_words_copy_2 = alloca i32, align 512
%out_words_copy_3 = alloca i32, align 512
call void @copy_in([4 x i32]* nonnull %0, i32* nonnull align 512 %in_words_copy_0, i32* nonnull align 512 %in_words_copy_1, i32* nonnull align 512 %in_words_copy_2, i32* nonnull align 512 %in_words_copy_3, [4 x i32]* nonnull %1, i32* nonnull align 512 %out_words_copy_0, i32* nonnull align 512 %out_words_copy_1, i32* nonnull align 512 %out_words_copy_2, i32* nonnull align 512 %out_words_copy_3)
call void @apatb_game_of_life_step_hw(i32* %in_words_copy_0, i32* %in_words_copy_1, i32* %in_words_copy_2, i32* %in_words_copy_3, i32* %out_words_copy_0, i32* %out_words_copy_1, i32* %out_words_copy_2, i32* %out_words_copy_3)
call void @copy_back([4 x i32]* %0, i32* %in_words_copy_0, i32* %in_words_copy_1, i32* %in_words_copy_2, i32* %in_words_copy_3, [4 x i32]* %1, i32* %out_words_copy_0, i32* %out_words_copy_1, i32* %out_words_copy_2, i32* %out_words_copy_3)
ret void
}
; Function Attrs: argmemonly noinline norecurse willreturn
define void @arraycpy_hls.p0a4i32([4 x i32]* "orig.arg.no"="0" %dst, [4 x i32]* readonly "orig.arg.no"="1" %src, i64 "orig.arg.no"="2" %num) local_unnamed_addr #1 {
entry:
%0 = icmp eq [4 x i32]* %src, null
%1 = icmp eq [4 x i32]* %dst, null
%2 = or i1 %1, %0
br i1 %2, label %ret, label %copy
copy: ; preds = %entry
%for.loop.cond1 = icmp sgt i64 %num, 0
br i1 %for.loop.cond1, label %for.loop.lr.ph, label %copy.split
for.loop.lr.ph: ; preds = %copy
br label %for.loop
for.loop: ; preds = %for.loop, %for.loop.lr.ph
%for.loop.idx2 = phi i64 [ 0, %for.loop.lr.ph ], [ %for.loop.idx.next, %for.loop ]
%dst.addr = getelementptr [4 x i32], [4 x i32]* %dst, i64 0, i64 %for.loop.idx2
%src.addr = getelementptr [4 x i32], [4 x i32]* %src, i64 0, i64 %for.loop.idx2
%3 = load i32, i32* %src.addr, align 4
store i32 %3, i32* %dst.addr, align 4
%for.loop.idx.next = add nuw nsw i64 %for.loop.idx2, 1
%exitcond = icmp ne i64 %for.loop.idx.next, %num
br i1 %exitcond, label %for.loop, label %copy.split
copy.split: ; preds = %for.loop, %copy
br label %ret
ret: ; preds = %copy.split, %entry
ret void
}
; Function Attrs: argmemonly noinline norecurse willreturn
define void @arraycpy_hls.p0a4i32.4.5(i32* "orig.arg.no"="0" "unpacked"="0.0" %dst_0, i32* "orig.arg.no"="0" "unpacked"="0.1" %dst_1, i32* "orig.arg.no"="0" "unpacked"="0.2" %dst_2, i32* "orig.arg.no"="0" "unpacked"="0.3" %dst_3, [4 x i32]* readonly "orig.arg.no"="1" %src, i64 "orig.arg.no"="2" %num) #1 {
entry:
%0 = icmp eq [4 x i32]* %src, null
%1 = icmp eq i32* %dst_0, null
%2 = or i1 %1, %0
br i1 %2, label %ret, label %copy
copy: ; preds = %entry
%for.loop.cond1 = icmp sgt i64 %num, 0
br i1 %for.loop.cond1, label %for.loop.lr.ph, label %copy.split
for.loop.lr.ph: ; preds = %copy
br label %for.loop
for.loop: ; preds = %dst.addr.exit, %for.loop.lr.ph
%for.loop.idx2 = phi i64 [ 0, %for.loop.lr.ph ], [ %for.loop.idx.next, %dst.addr.exit ]
%src.addr = getelementptr [4 x i32], [4 x i32]* %src, i64 0, i64 %for.loop.idx2
%3 = load i32, i32* %src.addr, align 4
switch i64 %for.loop.idx2, label %dst.addr.exit [
i64 0, label %dst.addr.case.0
i64 1, label %dst.addr.case.1
i64 2, label %dst.addr.case.2
i64 3, label %dst.addr.case.3
]
dst.addr.case.0: ; preds = %for.loop
store i32 %3, i32* %dst_0, align 4
br label %dst.addr.exit
dst.addr.case.1: ; preds = %for.loop
store i32 %3, i32* %dst_1, align 4
br label %dst.addr.exit
dst.addr.case.2: ; preds = %for.loop
store i32 %3, i32* %dst_2, align 4
br label %dst.addr.exit
dst.addr.case.3: ; preds = %for.loop
store i32 %3, i32* %dst_3, align 4
br label %dst.addr.exit
dst.addr.exit: ; preds = %dst.addr.case.3, %dst.addr.case.2, %dst.addr.case.1, %dst.addr.case.0, %for.loop
%for.loop.idx.next = add nuw nsw i64 %for.loop.idx2, 1
%exitcond = icmp ne i64 %for.loop.idx.next, %num
br i1 %exitcond, label %for.loop, label %copy.split
copy.split: ; preds = %dst.addr.exit, %copy
br label %ret
ret: ; preds = %copy.split, %entry
ret void
}
; Function Attrs: argmemonly noinline norecurse willreturn
define internal void @onebyonecpy_hls.p0a4i32.3.6(i32* noalias align 512 "orig.arg.no"="0" "unpacked"="0.0" %dst_0, i32* noalias align 512 "orig.arg.no"="0" "unpacked"="0.1" %dst_1, i32* noalias align 512 "orig.arg.no"="0" "unpacked"="0.2" %dst_2, i32* noalias align 512 "orig.arg.no"="0" "unpacked"="0.3" %dst_3, [4 x i32]* noalias readonly "orig.arg.no"="1" %src) #2 {
entry:
%0 = icmp eq i32* %dst_0, null
%1 = icmp eq [4 x i32]* %src, null
%2 = or i1 %0, %1
br i1 %2, label %ret, label %copy
copy: ; preds = %entry
call void @arraycpy_hls.p0a4i32.4.5(i32* nonnull %dst_0, i32* %dst_1, i32* %dst_2, i32* %dst_3, [4 x i32]* nonnull %src, i64 4)
br label %ret
ret: ; preds = %copy, %entry
ret void
}
; Function Attrs: argmemonly noinline norecurse willreturn
define internal void @copy_in([4 x i32]* noalias readonly "orig.arg.no"="0", i32* noalias align 512 "orig.arg.no"="1" "unpacked"="1.0" %_0, i32* noalias align 512 "orig.arg.no"="1" "unpacked"="1.1" %_1, i32* noalias align 512 "orig.arg.no"="1" "unpacked"="1.2" %_2, i32* noalias align 512 "orig.arg.no"="1" "unpacked"="1.3" %_3, [4 x i32]* noalias readonly "orig.arg.no"="2", i32* noalias align 512 "orig.arg.no"="3" "unpacked"="3.0" %_01, i32* noalias align 512 "orig.arg.no"="3" "unpacked"="3.1" %_12, i32* noalias align 512 "orig.arg.no"="3" "unpacked"="3.2" %_23, i32* noalias align 512 "orig.arg.no"="3" "unpacked"="3.3" %_34) #3 {
entry:
call void @onebyonecpy_hls.p0a4i32.3.6(i32* align 512 %_0, i32* align 512 %_1, i32* align 512 %_2, i32* align 512 %_3, [4 x i32]* %0)
call void @onebyonecpy_hls.p0a4i32.3.6(i32* align 512 %_01, i32* align 512 %_12, i32* align 512 %_23, i32* align 512 %_34, [4 x i32]* %1)
ret void
}
; Function Attrs: argmemonly noinline norecurse willreturn
define void @arraycpy_hls.p0a4i32.12.13([4 x i32]* "orig.arg.no"="0" %dst, i32* readonly "orig.arg.no"="1" "unpacked"="1.0" %src_0, i32* readonly "orig.arg.no"="1" "unpacked"="1.1" %src_1, i32* readonly "orig.arg.no"="1" "unpacked"="1.2" %src_2, i32* readonly "orig.arg.no"="1" "unpacked"="1.3" %src_3, i64 "orig.arg.no"="2" %num) #1 {
entry:
%0 = icmp eq i32* %src_0, null
%1 = icmp eq [4 x i32]* %dst, null
%2 = or i1 %1, %0
br i1 %2, label %ret, label %copy
copy: ; preds = %entry
%for.loop.cond1 = icmp sgt i64 %num, 0
br i1 %for.loop.cond1, label %for.loop.lr.ph, label %copy.split
for.loop.lr.ph: ; preds = %copy
br label %for.loop
for.loop: ; preds = %src.addr.exit, %for.loop.lr.ph
%for.loop.idx2 = phi i64 [ 0, %for.loop.lr.ph ], [ %for.loop.idx.next, %src.addr.exit ]
%dst.addr = getelementptr [4 x i32], [4 x i32]* %dst, i64 0, i64 %for.loop.idx2
switch i64 %for.loop.idx2, label %src.addr.exit [
i64 0, label %src.addr.case.0
i64 1, label %src.addr.case.1
i64 2, label %src.addr.case.2
i64 3, label %src.addr.case.3
]
src.addr.case.0: ; preds = %for.loop
%_0 = load i32, i32* %src_0, align 4
br label %src.addr.exit
src.addr.case.1: ; preds = %for.loop
%_1 = load i32, i32* %src_1, align 4
br label %src.addr.exit
src.addr.case.2: ; preds = %for.loop
%_2 = load i32, i32* %src_2, align 4
br label %src.addr.exit
src.addr.case.3: ; preds = %for.loop
%_3 = load i32, i32* %src_3, align 4
br label %src.addr.exit
src.addr.exit: ; preds = %src.addr.case.3, %src.addr.case.2, %src.addr.case.1, %src.addr.case.0, %for.loop
%3 = phi i32 [ %_0, %src.addr.case.0 ], [ %_1, %src.addr.case.1 ], [ %_2, %src.addr.case.2 ], [ %_3, %src.addr.case.3 ], [ undef, %for.loop ]
store i32 %3, i32* %dst.addr, align 4
%for.loop.idx.next = add nuw nsw i64 %for.loop.idx2, 1
%exitcond = icmp ne i64 %for.loop.idx.next, %num
br i1 %exitcond, label %for.loop, label %copy.split
copy.split: ; preds = %src.addr.exit, %copy
br label %ret
ret: ; preds = %copy.split, %entry
ret void
}
; Function Attrs: argmemonly noinline norecurse willreturn
define internal void @onebyonecpy_hls.p0a4i32.11.14([4 x i32]* noalias "orig.arg.no"="0" %dst, i32* noalias readonly align 512 "orig.arg.no"="1" "unpacked"="1.0" %src_0, i32* noalias readonly align 512 "orig.arg.no"="1" "unpacked"="1.1" %src_1, i32* noalias readonly align 512 "orig.arg.no"="1" "unpacked"="1.2" %src_2, i32* noalias readonly align 512 "orig.arg.no"="1" "unpacked"="1.3" %src_3) #2 {
entry:
%0 = icmp eq [4 x i32]* %dst, null
%1 = icmp eq i32* %src_0, null
%2 = or i1 %0, %1
br i1 %2, label %ret, label %copy
copy: ; preds = %entry
call void @arraycpy_hls.p0a4i32.12.13([4 x i32]* nonnull %dst, i32* nonnull %src_0, i32* %src_1, i32* %src_2, i32* %src_3, i64 4)
br label %ret
ret: ; preds = %copy, %entry
ret void
}
; Function Attrs: argmemonly noinline norecurse willreturn
define internal void @copy_out([4 x i32]* noalias "orig.arg.no"="0", i32* noalias readonly align 512 "orig.arg.no"="1" "unpacked"="1.0" %_0, i32* noalias readonly align 512 "orig.arg.no"="1" "unpacked"="1.1" %_1, i32* noalias readonly align 512 "orig.arg.no"="1" "unpacked"="1.2" %_2, i32* noalias readonly align 512 "orig.arg.no"="1" "unpacked"="1.3" %_3, [4 x i32]* noalias "orig.arg.no"="2", i32* noalias readonly align 512 "orig.arg.no"="3" "unpacked"="3.0" %_01, i32* noalias readonly align 512 "orig.arg.no"="3" "unpacked"="3.1" %_12, i32* noalias readonly align 512 "orig.arg.no"="3" "unpacked"="3.2" %_23, i32* noalias readonly align 512 "orig.arg.no"="3" "unpacked"="3.3" %_34) #4 {
entry:
call void @onebyonecpy_hls.p0a4i32.11.14([4 x i32]* %0, i32* align 512 %_0, i32* align 512 %_1, i32* align 512 %_2, i32* align 512 %_3)
call void @onebyonecpy_hls.p0a4i32.11.14([4 x i32]* %1, i32* align 512 %_01, i32* align 512 %_12, i32* align 512 %_23, i32* align 512 %_34)
ret void
}
declare i8* @malloc(i64)
declare void @free(i8*)
declare void @apatb_game_of_life_step_hw(i32*, i32*, i32*, i32*, i32*, i32*, i32*, i32*)
; Function Attrs: argmemonly noinline norecurse willreturn
define internal void @copy_back([4 x i32]* noalias "orig.arg.no"="0", i32* noalias readonly align 512 "orig.arg.no"="1" "unpacked"="1.0" %_0, i32* noalias readonly align 512 "orig.arg.no"="1" "unpacked"="1.1" %_1, i32* noalias readonly align 512 "orig.arg.no"="1" "unpacked"="1.2" %_2, i32* noalias readonly align 512 "orig.arg.no"="1" "unpacked"="1.3" %_3, [4 x i32]* noalias "orig.arg.no"="2", i32* noalias readonly align 512 "orig.arg.no"="3" "unpacked"="3.0" %_01, i32* noalias readonly align 512 "orig.arg.no"="3" "unpacked"="3.1" %_12, i32* noalias readonly align 512 "orig.arg.no"="3" "unpacked"="3.2" %_23, i32* noalias readonly align 512 "orig.arg.no"="3" "unpacked"="3.3" %_34) #4 {
entry:
call void @onebyonecpy_hls.p0a4i32.11.14([4 x i32]* %1, i32* align 512 %_01, i32* align 512 %_12, i32* align 512 %_23, i32* align 512 %_34)
ret void
}
declare void @game_of_life_step_hw_stub(i32* noalias nocapture nonnull readonly, i32* noalias nocapture nonnull)
define void @game_of_life_step_hw_stub_wrapper(i32*, i32*, i32*, i32*, i32*, i32*, i32*, i32*) #5 {
entry:
%8 = call i8* @malloc(i64 16)
%9 = bitcast i8* %8 to [4 x i32]*
%10 = call i8* @malloc(i64 16)
%11 = bitcast i8* %10 to [4 x i32]*
call void @copy_out([4 x i32]* %9, i32* %0, i32* %1, i32* %2, i32* %3, [4 x i32]* %11, i32* %4, i32* %5, i32* %6, i32* %7)
%12 = bitcast [4 x i32]* %9 to i32*
%13 = bitcast [4 x i32]* %11 to i32*
call void @game_of_life_step_hw_stub(i32* %12, i32* %13)
call void @copy_in([4 x i32]* %9, i32* %0, i32* %1, i32* %2, i32* %3, [4 x i32]* %11, i32* %4, i32* %5, i32* %6, i32* %7)
call void @free(i8* %8)
call void @free(i8* %10)
ret void
}
attributes #0 = { inaccessiblemem_or_argmemonly noinline willreturn "fpga.wrapper.func"="wrapper" }
attributes #1 = { argmemonly noinline norecurse willreturn "fpga.wrapper.func"="arraycpy_hls" }
attributes #2 = { argmemonly noinline norecurse willreturn "fpga.wrapper.func"="onebyonecpy_hls" }
attributes #3 = { argmemonly noinline norecurse willreturn "fpga.wrapper.func"="copyin" }
attributes #4 = { argmemonly noinline norecurse willreturn "fpga.wrapper.func"="copyout" }
attributes #5 = { "fpga.wrapper.func"="stub" }
!llvm.dbg.cu = !{}
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!llvm.module.flags = !{!1, !2, !3}
!blackbox_cfg = !{!4}
!datalayout.transforms.on.top = !{!5, !15}
!0 = !{!"clang version 7.0.0 "}
!1 = !{i32 2, !"Dwarf Version", i32 4}
!2 = !{i32 2, !"Debug Info Version", i32 3}
!3 = !{i32 1, !"wchar_size", i32 4}
!4 = !{}
!5 = !{!6, !8, !10}
!6 = !{!7}
!7 = !{!"0", [4 x i32]* null}
!8 = !{!9}
!9 = !{!"array_partition", !"type=Complete", !"dim=1"}
!10 = !{!11, !12, !13, !14}
!11 = !{!"0.0", i32* null}
!12 = !{!"0.1", i32* null}
!13 = !{!"0.2", i32* null}
!14 = !{!"0.3", i32* null}
!15 = !{!16, !8, !18}
!16 = !{!17}
!17 = !{!"1", [4 x i32]* null}
!18 = !{!19, !20, !21, !22}
!19 = !{!"1.0", i32* null}
!20 = !{!"1.1", i32* null}
!21 = !{!"1.2", i32* null}
!22 = !{!"1.3", i32* null}

7
Practicals/practical-3b/game_of_life_practical3b/game_of_life_practical3b/hls/.autopilot/db/autopilot.rtl.models.tcl Normal file
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@@ -0,0 +1,7 @@
set SynModuleInfo {
{SRCNAME game_of_life_step MODELNAME game_of_life_step RTLNAME game_of_life_step IS_TOP 1
SUBMODULES {
{MODELNAME game_of_life_step_AXILiteS_s_axi RTLNAME game_of_life_step_AXILiteS_s_axi BINDTYPE interface TYPE interface_s_axilite}
}
}
}

2
Practicals/practical-3b/game_of_life_practical3b/game_of_life_practical3b/hls/.autopilot/db/autopilot.rtl.models.txt Normal file
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@@ -0,0 +1,2 @@
game_of_life_step_AXILiteS_s_axi
game_of_life_step

0
Practicals/practical-3b/game_of_life_practical3b/game_of_life_practical3b/hls/.autopilot/db/clang.diag.xml Normal file
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22
Practicals/practical-3b/game_of_life_practical3b/game_of_life_practical3b/hls/.autopilot/db/cmplx.3.000.fe.link.json Normal file
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@@ -0,0 +1,22 @@
{
"0": {
"basicblocks": 56,
"calls": "",
"control_depth": 3,
"def_use_depth": 5,
"file": "gameoflife.cpp",
"fileloc": 5,
"instructions": 203,
"loads": {
"L": 3,
"T": 1
},
"memory_accesses": 12,
"name": "game_of_life_step",
"stores": {
"L": 3,
"T": 1
},
"total_instructions": 376
}
}

22
Practicals/practical-3b/game_of_life_practical3b/game_of_life_practical3b/hls/.autopilot/db/cmplx.3.001.fe.unroll-raw.json Normal file
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@@ -0,0 +1,22 @@
{
"0": {
"basicblocks": 4426,
"calls": "",
"control_depth": 0,
"def_use_depth": 3,
"file": "gameoflife.cpp",
"fileloc": 5,
"instructions": 12626,
"loads": {
"L": 1204,
"T": 100
},
"memory_accesses": 0,
"name": "game_of_life_step",
"stores": {
"L": 304,
"T": 4
},
"total_instructions": 12626
}
}

22
Practicals/practical-3b/game_of_life_practical3b/game_of_life_practical3b/hls/.autopilot/db/cmplx.3.002.fe.unroll-simplified.json Normal file
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@@ -0,0 +1,22 @@
{
"0": {
"basicblocks": 1,
"calls": "",
"control_depth": 0,
"def_use_depth": 37,
"file": "gameoflife.cpp",
"fileloc": 5,
"instructions": 3588,
"loads": {
"L": 145,
"T": 4
},
"memory_accesses": 0,
"name": "game_of_life_step",
"stores": {
"L": 200,
"T": 4
},
"total_instructions": 3588
}
}

22
Practicals/practical-3b/game_of_life_practical3b/game_of_life_practical3b/hls/.autopilot/db/cmplx.3.003.fe.inline-raw.json Normal file
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@@ -0,0 +1,22 @@
{
"0": {
"basicblocks": 1,
"calls": "",
"control_depth": 0,
"def_use_depth": 16,
"file": "gameoflife.cpp",
"fileloc": 5,
"instructions": 3492,
"loads": {
"L": 142,
"T": 4
},
"memory_accesses": 0,
"name": "game_of_life_step",
"stores": {
"L": 200,
"T": 4
},
"total_instructions": 3492
}
}

22
Practicals/practical-3b/game_of_life_practical3b/game_of_life_practical3b/hls/.autopilot/db/cmplx.3.004.fe.inline-simplified.json Normal file
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@@ -0,0 +1,22 @@
{
"0": {
"basicblocks": 1,
"calls": "",
"control_depth": 0,
"def_use_depth": 16,
"file": "gameoflife.cpp",
"fileloc": 5,
"instructions": 3492,
"loads": {
"L": 142,
"T": 4
},
"memory_accesses": 0,
"name": "game_of_life_step",
"stores": {
"L": 200,
"T": 4
},
"total_instructions": 3492
}
}

22
Practicals/practical-3b/game_of_life_practical3b/game_of_life_practical3b/hls/.autopilot/db/cmplx.3.005.fe.array-partition-raw.json Normal file
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@@ -0,0 +1,22 @@
{
"0": {
"basicblocks": 1,
"calls": "",
"control_depth": 0,
"def_use_depth": 16,
"file": "gameoflife.cpp",
"fileloc": 5,
"instructions": 3482,
"loads": {
"L": 141,
"T": 4
},
"memory_accesses": 0,
"name": "game_of_life_step",
"stores": {
"L": 200,
"T": 4
},
"total_instructions": 3482
}
}

20
Practicals/practical-3b/game_of_life_practical3b/game_of_life_practical3b/hls/.autopilot/db/cmplx.3.006.fe.array-partition-simplified.json Normal file
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@@ -0,0 +1,20 @@
{
"0": {
"basicblocks": 1,
"calls": "",
"control_depth": 0,
"def_use_depth": 16,
"file": "gameoflife.cpp",
"fileloc": 5,
"instructions": 2921,
"loads": {
"T": 4
},
"memory_accesses": 0,
"name": "game_of_life_step",
"stores": {
"T": 4
},
"total_instructions": 2921
}
}

20
Practicals/practical-3b/game_of_life_practical3b/game_of_life_practical3b/hls/.autopilot/db/cmplx.3.007.fe.aggregate.json Normal file
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@@ -0,0 +1,20 @@
{
"0": {
"basicblocks": 1,
"calls": "",
"control_depth": 0,
"def_use_depth": 16,
"file": "gameoflife.cpp",
"fileloc": 5,
"instructions": 2921,
"loads": {
"T": 4
},
"memory_accesses": 0,
"name": "game_of_life_step",
"stores": {
"T": 4
},
"total_instructions": 2921
}
}

20
Practicals/practical-3b/game_of_life_practical3b/game_of_life_practical3b/hls/.autopilot/db/cmplx.3.008.fe.array-reshape.json Normal file
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@@ -0,0 +1,20 @@
{
"0": {
"basicblocks": 1,
"calls": "",
"control_depth": 0,
"def_use_depth": 16,
"file": "gameoflife.cpp",
"fileloc": 5,
"instructions": 2921,
"loads": {
"T": 4
},
"memory_accesses": 0,
"name": "game_of_life_step",
"stores": {
"T": 4
},
"total_instructions": 2921
}
}

20
Practicals/practical-3b/game_of_life_practical3b/game_of_life_practical3b/hls/.autopilot/db/cmplx.3.009.fe.infer-access-pattern.json Normal file
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@@ -0,0 +1,20 @@
{
"0": {
"basicblocks": 1,
"calls": "",
"control_depth": 0,
"def_use_depth": 16,
"file": "gameoflife.cpp",
"fileloc": 5,
"instructions": 2921,
"loads": {
"T": 4
},
"memory_accesses": 0,
"name": "game_of_life_step",
"stores": {
"T": 4
},
"total_instructions": 2921
}
}

20
Practicals/practical-3b/game_of_life_practical3b/game_of_life_practical3b/hls/.autopilot/db/cmplx.3.010.fe.performance-prep.json Normal file
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@@ -0,0 +1,20 @@
{
"0": {
"basicblocks": 1,
"calls": "",
"control_depth": 0,
"def_use_depth": 16,
"file": "gameoflife.cpp",
"fileloc": 5,
"instructions": 2921,
"loads": {
"T": 4
},
"memory_accesses": 0,
"name": "game_of_life_step",
"stores": {
"T": 4
},
"total_instructions": 2921
}
}

20
Practicals/practical-3b/game_of_life_practical3b/game_of_life_practical3b/hls/.autopilot/db/cmplx.3.011.fe.performance-parallel.json Normal file
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@@ -0,0 +1,20 @@
{
"0": {
"basicblocks": 1,
"calls": "",
"control_depth": 0,
"def_use_depth": 16,
"file": "gameoflife.cpp",
"fileloc": 5,
"instructions": 2921,
"loads": {
"T": 4
},
"memory_accesses": 0,
"name": "game_of_life_step",
"stores": {
"T": 4
},
"total_instructions": 2921
}
}

20
Practicals/practical-3b/game_of_life_practical3b/game_of_life_practical3b/hls/.autopilot/db/cmplx.3.012.fe.performance-array-partition-raw.json Normal file
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@@ -0,0 +1,20 @@
{
"0": {
"basicblocks": 1,
"calls": "",
"control_depth": 0,
"def_use_depth": 16,
"file": "gameoflife.cpp",
"fileloc": 5,
"instructions": 2921,
"loads": {
"T": 4
},
"memory_accesses": 0,
"name": "game_of_life_step",
"stores": {
"T": 4
},
"total_instructions": 2921
}
}

20
Practicals/practical-3b/game_of_life_practical3b/game_of_life_practical3b/hls/.autopilot/db/cmplx.3.013.fe.performance-final.json Normal file
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@@ -0,0 +1,20 @@
{
"0": {
"basicblocks": 1,
"calls": "",
"control_depth": 0,
"def_use_depth": 16,
"file": "gameoflife.cpp",
"fileloc": 5,
"instructions": 2921,
"loads": {
"T": 4
},
"memory_accesses": 0,
"name": "game_of_life_step",
"stores": {
"T": 4
},
"total_instructions": 2921
}
}

20
Practicals/practical-3b/game_of_life_practical3b/game_of_life_practical3b/hls/.autopilot/db/cmplx.3.014.fe.simplify.json Normal file
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@@ -0,0 +1,20 @@
{
"0": {
"basicblocks": 1,
"calls": "",
"control_depth": 0,
"def_use_depth": 16,
"file": "gameoflife.cpp",
"fileloc": 5,
"instructions": 2921,
"loads": {
"T": 4
},
"memory_accesses": 0,
"name": "game_of_life_step",
"stores": {
"T": 4
},
"total_instructions": 2921
}
}

20
Practicals/practical-3b/game_of_life_practical3b/game_of_life_practical3b/hls/.autopilot/db/cmplx.3.015.fe.lowering.json Normal file
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@@ -0,0 +1,20 @@
{
"0": {
"basicblocks": 1,
"calls": "",
"control_depth": 0,
"def_use_depth": 16,
"file": "gameoflife.cpp",
"fileloc": 5,
"instructions": 2937,
"loads": {
"T": 4
},
"memory_accesses": 0,
"name": "game_of_life_step",
"stores": {
"T": 4
},
"total_instructions": 2937
}
}

20
Practicals/practical-3b/game_of_life_practical3b/game_of_life_practical3b/hls/.autopilot/db/cmplx.3.016.fe.opt.json Normal file
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@@ -0,0 +1,20 @@
{
"0": {
"basicblocks": 1,
"calls": "",
"control_depth": 0,
"def_use_depth": 16,
"file": "gameoflife.cpp",
"fileloc": 5,
"instructions": 2938,
"loads": {
"T": 4
},
"memory_accesses": 0,
"name": "game_of_life_step",
"stores": {
"T": 4
},
"total_instructions": 2938
}
}

14
Practicals/practical-3b/game_of_life_practical3b/game_of_life_practical3b/hls/.autopilot/db/cmplx.5.0.fe.end.json Normal file
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@@ -0,0 +1,14 @@
{
"0": {
"name": "game_of_life_step",
"file": "gameoflife.cpp",
"fileloc": "5",
"instructions": "1714",
"total_instructions": "1714",
"calls": "",
"basicblocks": "1",
"memory_accesses": "0",
"control_depth": "0",
"def_use_depth": "10"
}
}

77
Practicals/practical-3b/game_of_life_practical3b/game_of_life_practical3b/hls/.autopilot/db/coregen/AXILiteS.h Normal file
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@@ -0,0 +1,77 @@
// 0x00 : Control signals
// bit 0 - ap_start (Read/Write/COH)
// bit 1 - ap_done (Read/COR)
// bit 2 - ap_idle (Read)
// bit 3 - ap_ready (Read/COR)
// bit 7 - auto_restart (Read/Write)
// bit 9 - interrupt (Read)
// others - reserved
// 0x04 : Global Interrupt Enable Register
// bit 0 - Global Interrupt Enable (Read/Write)
// others - reserved
// 0x08 : IP Interrupt Enable Register (Read/Write)
// bit 0 - enable ap_done interrupt (Read/Write)
// bit 1 - enable ap_ready interrupt (Read/Write)
// others - reserved
// 0x0c : IP Interrupt Status Register (Read/TOW)
// bit 0 - ap_done (Read/TOW)
// bit 1 - ap_ready (Read/TOW)
// others - reserved
// 0x10 : Data signal of in_words_0
// bit 31~0 - in_words_0[31:0] (Read/Write)
// 0x14 : reserved
// 0x18 : Data signal of in_words_1
// bit 31~0 - in_words_1[31:0] (Read/Write)
// 0x1c : reserved
// 0x20 : Data signal of in_words_2
// bit 31~0 - in_words_2[31:0] (Read/Write)
// 0x24 : reserved
// 0x28 : Data signal of in_words_3
// bit 31~0 - in_words_3[31:0] (Read/Write)
// 0x2c : reserved
// 0x30 : Data signal of out_words_0
// bit 31~0 - out_words_0[31:0] (Read)
// 0x34 : Control signal of out_words_0
// bit 0 - out_words_0_ap_vld (Read/COR)
// others - reserved
// 0x40 : Data signal of out_words_1
// bit 31~0 - out_words_1[31:0] (Read)
// 0x44 : Control signal of out_words_1
// bit 0 - out_words_1_ap_vld (Read/COR)
// others - reserved
// 0x50 : Data signal of out_words_2
// bit 31~0 - out_words_2[31:0] (Read)
// 0x54 : Control signal of out_words_2
// bit 0 - out_words_2_ap_vld (Read/COR)
// others - reserved
// 0x60 : Data signal of out_words_3
// bit 31~0 - out_words_3[31:0] (Read)
// 0x64 : Control signal of out_words_3
// bit 0 - out_words_3_ap_vld (Read/COR)
// others - reserved
// (SC = Self Clear, COR = Clear on Read, TOW = Toggle on Write, COH = Clear on Handshake)
#define AXILITES_ADDR_AP_CTRL 0x00
#define AXILITES_ADDR_GIE 0x04
#define AXILITES_ADDR_IER 0x08
#define AXILITES_ADDR_ISR 0x0c
#define AXILITES_ADDR_IN_WORDS_0_DATA 0x10
#define AXILITES_BITS_IN_WORDS_0_DATA 32
#define AXILITES_ADDR_IN_WORDS_1_DATA 0x18
#define AXILITES_BITS_IN_WORDS_1_DATA 32
#define AXILITES_ADDR_IN_WORDS_2_DATA 0x20
#define AXILITES_BITS_IN_WORDS_2_DATA 32
#define AXILITES_ADDR_IN_WORDS_3_DATA 0x28
#define AXILITES_BITS_IN_WORDS_3_DATA 32
#define AXILITES_ADDR_OUT_WORDS_0_DATA 0x30
#define AXILITES_BITS_OUT_WORDS_0_DATA 32
#define AXILITES_ADDR_OUT_WORDS_0_CTRL 0x34
#define AXILITES_ADDR_OUT_WORDS_1_DATA 0x40
#define AXILITES_BITS_OUT_WORDS_1_DATA 32
#define AXILITES_ADDR_OUT_WORDS_1_CTRL 0x44
#define AXILITES_ADDR_OUT_WORDS_2_DATA 0x50
#define AXILITES_BITS_OUT_WORDS_2_DATA 32
#define AXILITES_ADDR_OUT_WORDS_2_CTRL 0x54
#define AXILITES_ADDR_OUT_WORDS_3_DATA 0x60
#define AXILITES_BITS_OUT_WORDS_3_DATA 32
#define AXILITES_ADDR_OUT_WORDS_3_CTRL 0x64

4
Practicals/practical-3b/game_of_life_practical3b/game_of_life_practical3b/hls/.autopilot/db/coregen/AXILiteS.slave.tcl Normal file
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dict set slaves AXILiteS {ports {in_words_0 {type i_ap_none width 32} in_words_1 {type i_ap_none width 32} in_words_2 {type i_ap_none width 32} in_words_3 {type i_ap_none width 32} out_words_0 {type o_ap_vld width 32} out_words_1 {type o_ap_vld width 32} out_words_2 {type o_ap_vld width 32} out_words_3 {type o_ap_vld width 32} ap_start {type ap_ctrl width 1} ap_done {type ap_ctrl width 1} ap_ready {type ap_ctrl width 1} ap_idle {type ap_ctrl width 1}} mems {} has_ctrl 1}
set datawidth 32
set addrwidth 64
set intr_clr_mode TOW

612
Practicals/practical-3b/game_of_life_practical3b/game_of_life_practical3b/hls/.autopilot/db/coregen/game_of_life_step_AXILiteS_s_axi.v Normal file
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// ==============================================================
// Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2025.1 (64-bit)
// Tool Version Limit: 2025.05
// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
// Copyright 2022-2025 Advanced Micro Devices, Inc. All Rights Reserved.
//
// ==============================================================
`timescale 1ns/1ps
module game_of_life_step_AXILiteS_s_axi
#(parameter
C_S_AXI_ADDR_WIDTH = 7,
C_S_AXI_DATA_WIDTH = 32
)(
input wire ACLK,
input wire ARESET,
input wire ACLK_EN,
input wire [C_S_AXI_ADDR_WIDTH-1:0] AWADDR,
input wire AWVALID,
output wire AWREADY,
input wire [C_S_AXI_DATA_WIDTH-1:0] WDATA,
input wire [C_S_AXI_DATA_WIDTH/8-1:0] WSTRB,
input wire WVALID,
output wire WREADY,
output wire [1:0] BRESP,
output wire BVALID,
input wire BREADY,
input wire [C_S_AXI_ADDR_WIDTH-1:0] ARADDR,
input wire ARVALID,
output wire ARREADY,
output wire [C_S_AXI_DATA_WIDTH-1:0] RDATA,
output wire [1:0] RRESP,
output wire RVALID,
input wire RREADY,
output wire interrupt,
output wire [31:0] in_words_0,
output wire [31:0] in_words_1,
output wire [31:0] in_words_2,
output wire [31:0] in_words_3,
input wire [31:0] out_words_0,
input wire out_words_0_ap_vld,
input wire [31:0] out_words_1,
input wire out_words_1_ap_vld,
input wire [31:0] out_words_2,
input wire out_words_2_ap_vld,
input wire [31:0] out_words_3,
input wire out_words_3_ap_vld,
output wire ap_start,
input wire ap_done,
input wire ap_ready,
input wire ap_idle
);
//------------------------Address Info-------------------
// Protocol Used: ap_ctrl_hs
//
// 0x00 : Control signals
// bit 0 - ap_start (Read/Write/COH)
// bit 1 - ap_done (Read/COR)
// bit 2 - ap_idle (Read)
// bit 3 - ap_ready (Read/COR)
// bit 7 - auto_restart (Read/Write)
// bit 9 - interrupt (Read)
// others - reserved
// 0x04 : Global Interrupt Enable Register
// bit 0 - Global Interrupt Enable (Read/Write)
// others - reserved
// 0x08 : IP Interrupt Enable Register (Read/Write)
// bit 0 - enable ap_done interrupt (Read/Write)
// bit 1 - enable ap_ready interrupt (Read/Write)
// others - reserved
// 0x0c : IP Interrupt Status Register (Read/TOW)
// bit 0 - ap_done (Read/TOW)
// bit 1 - ap_ready (Read/TOW)
// others - reserved
// 0x10 : Data signal of in_words_0
// bit 31~0 - in_words_0[31:0] (Read/Write)
// 0x14 : reserved
// 0x18 : Data signal of in_words_1
// bit 31~0 - in_words_1[31:0] (Read/Write)
// 0x1c : reserved
// 0x20 : Data signal of in_words_2
// bit 31~0 - in_words_2[31:0] (Read/Write)
// 0x24 : reserved
// 0x28 : Data signal of in_words_3
// bit 31~0 - in_words_3[31:0] (Read/Write)
// 0x2c : reserved
// 0x30 : Data signal of out_words_0
// bit 31~0 - out_words_0[31:0] (Read)
// 0x34 : Control signal of out_words_0
// bit 0 - out_words_0_ap_vld (Read/COR)
// others - reserved
// 0x40 : Data signal of out_words_1
// bit 31~0 - out_words_1[31:0] (Read)
// 0x44 : Control signal of out_words_1
// bit 0 - out_words_1_ap_vld (Read/COR)
// others - reserved
// 0x50 : Data signal of out_words_2
// bit 31~0 - out_words_2[31:0] (Read)
// 0x54 : Control signal of out_words_2
// bit 0 - out_words_2_ap_vld (Read/COR)
// others - reserved
// 0x60 : Data signal of out_words_3
// bit 31~0 - out_words_3[31:0] (Read)
// 0x64 : Control signal of out_words_3
// bit 0 - out_words_3_ap_vld (Read/COR)
// others - reserved
// (SC = Self Clear, COR = Clear on Read, TOW = Toggle on Write, COH = Clear on Handshake)
//------------------------Parameter----------------------
localparam
ADDR_AP_CTRL = 7'h00,
ADDR_GIE = 7'h04,
ADDR_IER = 7'h08,
ADDR_ISR = 7'h0c,
ADDR_IN_WORDS_0_DATA_0 = 7'h10,
ADDR_IN_WORDS_0_CTRL = 7'h14,
ADDR_IN_WORDS_1_DATA_0 = 7'h18,
ADDR_IN_WORDS_1_CTRL = 7'h1c,
ADDR_IN_WORDS_2_DATA_0 = 7'h20,
ADDR_IN_WORDS_2_CTRL = 7'h24,
ADDR_IN_WORDS_3_DATA_0 = 7'h28,
ADDR_IN_WORDS_3_CTRL = 7'h2c,
ADDR_OUT_WORDS_0_DATA_0 = 7'h30,
ADDR_OUT_WORDS_0_CTRL = 7'h34,
ADDR_OUT_WORDS_1_DATA_0 = 7'h40,
ADDR_OUT_WORDS_1_CTRL = 7'h44,
ADDR_OUT_WORDS_2_DATA_0 = 7'h50,
ADDR_OUT_WORDS_2_CTRL = 7'h54,
ADDR_OUT_WORDS_3_DATA_0 = 7'h60,
ADDR_OUT_WORDS_3_CTRL = 7'h64,
WRIDLE = 2'd0,
WRDATA = 2'd1,
WRRESP = 2'd2,
WRRESET = 2'd3,
RDIDLE = 2'd0,
RDDATA = 2'd1,
RDRESET = 2'd2,
ADDR_BITS = 7;
//------------------------Local signal-------------------
reg [1:0] wstate = WRRESET;
reg [1:0] wnext;
reg [ADDR_BITS-1:0] waddr;
wire [C_S_AXI_DATA_WIDTH-1:0] wmask;
wire aw_hs;
wire w_hs;
reg [1:0] rstate = RDRESET;
reg [1:0] rnext;
reg [C_S_AXI_DATA_WIDTH-1:0] rdata;
wire ar_hs;
wire [ADDR_BITS-1:0] raddr;
// internal registers
reg int_ap_idle = 1'b0;
reg int_ap_ready = 1'b0;
wire task_ap_ready;
reg int_ap_done = 1'b0;
wire task_ap_done;
reg int_task_ap_done = 1'b0;
reg int_ap_start = 1'b0;
reg int_interrupt = 1'b0;
reg int_auto_restart = 1'b0;
reg auto_restart_status = 1'b0;
wire auto_restart_done;
reg int_gie = 1'b0;
reg [1:0] int_ier = 2'b0;
reg [1:0] int_isr = 2'b0;
reg [31:0] int_in_words_0 = 'b0;
reg [31:0] int_in_words_1 = 'b0;
reg [31:0] int_in_words_2 = 'b0;
reg [31:0] int_in_words_3 = 'b0;
reg int_out_words_0_ap_vld;
reg [31:0] int_out_words_0 = 'b0;
reg int_out_words_1_ap_vld;
reg [31:0] int_out_words_1 = 'b0;
reg int_out_words_2_ap_vld;
reg [31:0] int_out_words_2 = 'b0;
reg int_out_words_3_ap_vld;
reg [31:0] int_out_words_3 = 'b0;
//------------------------Instantiation------------------
//------------------------AXI write fsm------------------
assign AWREADY = (wstate == WRIDLE);
assign WREADY = (wstate == WRDATA);
assign BVALID = (wstate == WRRESP);
assign BRESP = 2'b00; // OKAY
assign wmask = { {8{WSTRB[3]}}, {8{WSTRB[2]}}, {8{WSTRB[1]}}, {8{WSTRB[0]}} };
assign aw_hs = AWVALID & AWREADY;
assign w_hs = WVALID & WREADY;
// wstate
always @(posedge ACLK) begin
if (ARESET)
wstate <= WRRESET;
else if (ACLK_EN)
wstate <= wnext;
end
// wnext
always @(*) begin
case (wstate)
WRIDLE:
if (AWVALID)
wnext = WRDATA;
else
wnext = WRIDLE;
WRDATA:
if (WVALID)
wnext = WRRESP;
else
wnext = WRDATA;
WRRESP:
if (BREADY & BVALID)
wnext = WRIDLE;
else
wnext = WRRESP;
default:
wnext = WRIDLE;
endcase
end
// waddr
always @(posedge ACLK) begin
if (ACLK_EN) begin
if (aw_hs)
waddr <= {AWADDR[ADDR_BITS-1:2], {2{1'b0}}};
end
end
//------------------------AXI read fsm-------------------
assign ARREADY = (rstate == RDIDLE);
assign RDATA = rdata;
assign RRESP = 2'b00; // OKAY
assign RVALID = (rstate == RDDATA);
assign ar_hs = ARVALID & ARREADY;
assign raddr = ARADDR[ADDR_BITS-1:0];
// rstate
always @(posedge ACLK) begin
if (ARESET)
rstate <= RDRESET;
else if (ACLK_EN)
rstate <= rnext;
end
// rnext
always @(*) begin
case (rstate)
RDIDLE:
if (ARVALID)
rnext = RDDATA;
else
rnext = RDIDLE;
RDDATA:
if (RREADY & RVALID)
rnext = RDIDLE;
else
rnext = RDDATA;
default:
rnext = RDIDLE;
endcase
end
// rdata
always @(posedge ACLK) begin
if (ACLK_EN) begin
if (ar_hs) begin
rdata <= 'b0;
case (raddr)
ADDR_AP_CTRL: begin
rdata[0] <= int_ap_start;
rdata[1] <= int_task_ap_done;
rdata[2] <= int_ap_idle;
rdata[3] <= int_ap_ready;
rdata[7] <= int_auto_restart;
rdata[9] <= int_interrupt;
end
ADDR_GIE: begin
rdata <= int_gie;
end
ADDR_IER: begin
rdata <= int_ier;
end
ADDR_ISR: begin
rdata <= int_isr;
end
ADDR_IN_WORDS_0_DATA_0: begin
rdata <= int_in_words_0[31:0];
end
ADDR_IN_WORDS_1_DATA_0: begin
rdata <= int_in_words_1[31:0];
end
ADDR_IN_WORDS_2_DATA_0: begin
rdata <= int_in_words_2[31:0];
end
ADDR_IN_WORDS_3_DATA_0: begin
rdata <= int_in_words_3[31:0];
end
ADDR_OUT_WORDS_0_DATA_0: begin
rdata <= int_out_words_0[31:0];
end
ADDR_OUT_WORDS_0_CTRL: begin
rdata[0] <= int_out_words_0_ap_vld;
end
ADDR_OUT_WORDS_1_DATA_0: begin
rdata <= int_out_words_1[31:0];
end
ADDR_OUT_WORDS_1_CTRL: begin
rdata[0] <= int_out_words_1_ap_vld;
end
ADDR_OUT_WORDS_2_DATA_0: begin
rdata <= int_out_words_2[31:0];
end
ADDR_OUT_WORDS_2_CTRL: begin
rdata[0] <= int_out_words_2_ap_vld;
end
ADDR_OUT_WORDS_3_DATA_0: begin
rdata <= int_out_words_3[31:0];
end
ADDR_OUT_WORDS_3_CTRL: begin
rdata[0] <= int_out_words_3_ap_vld;
end
endcase
end
end
end
//------------------------Register logic-----------------
assign interrupt = int_interrupt;
assign ap_start = int_ap_start;
assign task_ap_done = (ap_done && !auto_restart_status) || auto_restart_done;
assign task_ap_ready = ap_ready && !int_auto_restart;
assign auto_restart_done = auto_restart_status && (ap_idle && !int_ap_idle);
assign in_words_0 = int_in_words_0;
assign in_words_1 = int_in_words_1;
assign in_words_2 = int_in_words_2;
assign in_words_3 = int_in_words_3;
// int_interrupt
always @(posedge ACLK) begin
if (ARESET)
int_interrupt <= 1'b0;
else if (ACLK_EN) begin
if (int_gie && (|int_isr))
int_interrupt <= 1'b1;
else
int_interrupt <= 1'b0;
end
end
// int_ap_start
always @(posedge ACLK) begin
if (ARESET)
int_ap_start <= 1'b0;
else if (ACLK_EN) begin
if (w_hs && waddr == ADDR_AP_CTRL && WSTRB[0] && WDATA[0])
int_ap_start <= 1'b1;
else if (ap_ready)
int_ap_start <= int_auto_restart; // clear on handshake/auto restart
end
end
// int_ap_done
always @(posedge ACLK) begin
if (ARESET)
int_ap_done <= 1'b0;
else if (ACLK_EN) begin
int_ap_done <= ap_done;
end
end
// int_task_ap_done
always @(posedge ACLK) begin
if (ARESET)
int_task_ap_done <= 1'b0;
else if (ACLK_EN) begin
if (task_ap_done)
int_task_ap_done <= 1'b1;
else if (ar_hs && raddr == ADDR_AP_CTRL)
int_task_ap_done <= 1'b0; // clear on read
end
end
// int_ap_idle
always @(posedge ACLK) begin
if (ARESET)
int_ap_idle <= 1'b0;
else if (ACLK_EN) begin
int_ap_idle <= ap_idle;
end
end
// int_ap_ready
always @(posedge ACLK) begin
if (ARESET)
int_ap_ready <= 1'b0;
else if (ACLK_EN) begin
if (task_ap_ready)
int_ap_ready <= 1'b1;
else if (ar_hs && raddr == ADDR_AP_CTRL)
int_ap_ready <= 1'b0;
end
end
// int_auto_restart
always @(posedge ACLK) begin
if (ARESET)
int_auto_restart <= 1'b0;
else if (ACLK_EN) begin
if (w_hs && waddr == ADDR_AP_CTRL && WSTRB[0])
int_auto_restart <= WDATA[7];
end
end
// auto_restart_status
always @(posedge ACLK) begin
if (ARESET)
auto_restart_status <= 1'b0;
else if (ACLK_EN) begin
if (int_auto_restart)
auto_restart_status <= 1'b1;
else if (ap_idle)
auto_restart_status <= 1'b0;
end
end
// int_gie
always @(posedge ACLK) begin
if (ARESET)
int_gie <= 1'b0;
else if (ACLK_EN) begin
if (w_hs && waddr == ADDR_GIE && WSTRB[0])
int_gie <= WDATA[0];
end
end
// int_ier
always @(posedge ACLK) begin
if (ARESET)
int_ier <= 1'b0;
else if (ACLK_EN) begin
if (w_hs && waddr == ADDR_IER && WSTRB[0])
int_ier <= WDATA[1:0];
end
end
// int_isr[0]
always @(posedge ACLK) begin
if (ARESET)
int_isr[0] <= 1'b0;
else if (ACLK_EN) begin
if (int_ier[0] & ap_done)
int_isr[0] <= 1'b1;
else if (w_hs && waddr == ADDR_ISR && WSTRB[0])
int_isr[0] <= int_isr[0] ^ WDATA[0]; // toggle on write
end
end
// int_isr[1]
always @(posedge ACLK) begin
if (ARESET)
int_isr[1] <= 1'b0;
else if (ACLK_EN) begin
if (int_ier[1] & ap_ready)
int_isr[1] <= 1'b1;
else if (w_hs && waddr == ADDR_ISR && WSTRB[0])
int_isr[1] <= int_isr[1] ^ WDATA[1]; // toggle on write
end
end
// int_in_words_0[31:0]
always @(posedge ACLK) begin
if (ARESET)
int_in_words_0[31:0] <= 0;
else if (ACLK_EN) begin
if (w_hs && waddr == ADDR_IN_WORDS_0_DATA_0)
int_in_words_0[31:0] <= (WDATA[31:0] & wmask) | (int_in_words_0[31:0] & ~wmask);
end
end
// int_in_words_1[31:0]
always @(posedge ACLK) begin
if (ARESET)
int_in_words_1[31:0] <= 0;
else if (ACLK_EN) begin
if (w_hs && waddr == ADDR_IN_WORDS_1_DATA_0)
int_in_words_1[31:0] <= (WDATA[31:0] & wmask) | (int_in_words_1[31:0] & ~wmask);
end
end
// int_in_words_2[31:0]
always @(posedge ACLK) begin
if (ARESET)
int_in_words_2[31:0] <= 0;
else if (ACLK_EN) begin
if (w_hs && waddr == ADDR_IN_WORDS_2_DATA_0)
int_in_words_2[31:0] <= (WDATA[31:0] & wmask) | (int_in_words_2[31:0] & ~wmask);
end
end
// int_in_words_3[31:0]
always @(posedge ACLK) begin
if (ARESET)
int_in_words_3[31:0] <= 0;
else if (ACLK_EN) begin
if (w_hs && waddr == ADDR_IN_WORDS_3_DATA_0)
int_in_words_3[31:0] <= (WDATA[31:0] & wmask) | (int_in_words_3[31:0] & ~wmask);
end
end
// int_out_words_0
always @(posedge ACLK) begin
if (ARESET)
int_out_words_0 <= 0;
else if (ACLK_EN) begin
if (out_words_0_ap_vld)
int_out_words_0 <= out_words_0;
end
end
// int_out_words_0_ap_vld
always @(posedge ACLK) begin
if (ARESET)
int_out_words_0_ap_vld <= 1'b0;
else if (ACLK_EN) begin
if (out_words_0_ap_vld)
int_out_words_0_ap_vld <= 1'b1;
else if (ar_hs && raddr == ADDR_OUT_WORDS_0_CTRL)
int_out_words_0_ap_vld <= 1'b0; // clear on read
end
end
// int_out_words_1
always @(posedge ACLK) begin
if (ARESET)
int_out_words_1 <= 0;
else if (ACLK_EN) begin
if (out_words_1_ap_vld)
int_out_words_1 <= out_words_1;
end
end
// int_out_words_1_ap_vld
always @(posedge ACLK) begin
if (ARESET)
int_out_words_1_ap_vld <= 1'b0;
else if (ACLK_EN) begin
if (out_words_1_ap_vld)
int_out_words_1_ap_vld <= 1'b1;
else if (ar_hs && raddr == ADDR_OUT_WORDS_1_CTRL)
int_out_words_1_ap_vld <= 1'b0; // clear on read
end
end
// int_out_words_2
always @(posedge ACLK) begin
if (ARESET)
int_out_words_2 <= 0;
else if (ACLK_EN) begin
if (out_words_2_ap_vld)
int_out_words_2 <= out_words_2;
end
end
// int_out_words_2_ap_vld
always @(posedge ACLK) begin
if (ARESET)
int_out_words_2_ap_vld <= 1'b0;
else if (ACLK_EN) begin
if (out_words_2_ap_vld)
int_out_words_2_ap_vld <= 1'b1;
else if (ar_hs && raddr == ADDR_OUT_WORDS_2_CTRL)
int_out_words_2_ap_vld <= 1'b0; // clear on read
end
end
// int_out_words_3
always @(posedge ACLK) begin
if (ARESET)
int_out_words_3 <= 0;
else if (ACLK_EN) begin
if (out_words_3_ap_vld)
int_out_words_3 <= out_words_3;
end
end
// int_out_words_3_ap_vld
always @(posedge ACLK) begin
if (ARESET)
int_out_words_3_ap_vld <= 1'b0;
else if (ACLK_EN) begin
if (out_words_3_ap_vld)
int_out_words_3_ap_vld <= 1'b1;
else if (ar_hs && raddr == ADDR_OUT_WORDS_3_CTRL)
int_out_words_3_ap_vld <= 1'b0; // clear on read
end
end
//synthesis translate_off
always @(posedge ACLK) begin
if (ACLK_EN) begin
if (int_gie & ~int_isr[0] & int_ier[0] & ap_done)
$display ("// Interrupt Monitor : interrupt for ap_done detected @ \"%0t\"", $time);
if (int_gie & ~int_isr[1] & int_ier[1] & ap_ready)
$display ("// Interrupt Monitor : interrupt for ap_ready detected @ \"%0t\"", $time);
end
end
//synthesis translate_on
//------------------------Memory logic-------------------
endmodule

688
Practicals/practical-3b/game_of_life_practical3b/game_of_life_practical3b/hls/.autopilot/db/coregen/game_of_life_step_AXILiteS_s_axi.vhd Normal file
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@@ -0,0 +1,688 @@
-- ==============================================================
-- Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2025.1 (64-bit)
-- Tool Version Limit: 2025.05
-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
-- Copyright 2022-2025 Advanced Micro Devices, Inc. All Rights Reserved.
--
-- ==============================================================
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
entity game_of_life_step_AXILiteS_s_axi is
generic (
C_S_AXI_ADDR_WIDTH : INTEGER := 7;
C_S_AXI_DATA_WIDTH : INTEGER := 32);
port (
ACLK :in STD_LOGIC;
ARESET :in STD_LOGIC;
ACLK_EN :in STD_LOGIC;
AWADDR :in STD_LOGIC_VECTOR(C_S_AXI_ADDR_WIDTH-1 downto 0);
AWVALID :in STD_LOGIC;
AWREADY :out STD_LOGIC;
WDATA :in STD_LOGIC_VECTOR(C_S_AXI_DATA_WIDTH-1 downto 0);
WSTRB :in STD_LOGIC_VECTOR(C_S_AXI_DATA_WIDTH/8-1 downto 0);
WVALID :in STD_LOGIC;
WREADY :out STD_LOGIC;
BRESP :out STD_LOGIC_VECTOR(1 downto 0);
BVALID :out STD_LOGIC;
BREADY :in STD_LOGIC;
ARADDR :in STD_LOGIC_VECTOR(C_S_AXI_ADDR_WIDTH-1 downto 0);
ARVALID :in STD_LOGIC;
ARREADY :out STD_LOGIC;
RDATA :out STD_LOGIC_VECTOR(C_S_AXI_DATA_WIDTH-1 downto 0);
RRESP :out STD_LOGIC_VECTOR(1 downto 0);
RVALID :out STD_LOGIC;
RREADY :in STD_LOGIC;
interrupt :out STD_LOGIC;
in_words_0 :out STD_LOGIC_VECTOR(31 downto 0);
in_words_1 :out STD_LOGIC_VECTOR(31 downto 0);
in_words_2 :out STD_LOGIC_VECTOR(31 downto 0);
in_words_3 :out STD_LOGIC_VECTOR(31 downto 0);
out_words_0 :in STD_LOGIC_VECTOR(31 downto 0);
out_words_0_ap_vld :in STD_LOGIC;
out_words_1 :in STD_LOGIC_VECTOR(31 downto 0);
out_words_1_ap_vld :in STD_LOGIC;
out_words_2 :in STD_LOGIC_VECTOR(31 downto 0);
out_words_2_ap_vld :in STD_LOGIC;
out_words_3 :in STD_LOGIC_VECTOR(31 downto 0);
out_words_3_ap_vld :in STD_LOGIC;
ap_start :out STD_LOGIC;
ap_done :in STD_LOGIC;
ap_ready :in STD_LOGIC;
ap_idle :in STD_LOGIC
);
end entity game_of_life_step_AXILiteS_s_axi;
-- ------------------------Address Info-------------------
-- Protocol Used: ap_ctrl_hs
--
-- 0x00 : Control signals
-- bit 0 - ap_start (Read/Write/COH)
-- bit 1 - ap_done (Read/COR)
-- bit 2 - ap_idle (Read)
-- bit 3 - ap_ready (Read/COR)
-- bit 7 - auto_restart (Read/Write)
-- bit 9 - interrupt (Read)
-- others - reserved
-- 0x04 : Global Interrupt Enable Register
-- bit 0 - Global Interrupt Enable (Read/Write)
-- others - reserved
-- 0x08 : IP Interrupt Enable Register (Read/Write)
-- bit 0 - enable ap_done interrupt (Read/Write)
-- bit 1 - enable ap_ready interrupt (Read/Write)
-- others - reserved
-- 0x0c : IP Interrupt Status Register (Read/TOW)
-- bit 0 - ap_done (Read/TOW)
-- bit 1 - ap_ready (Read/TOW)
-- others - reserved
-- 0x10 : Data signal of in_words_0
-- bit 31~0 - in_words_0[31:0] (Read/Write)
-- 0x14 : reserved
-- 0x18 : Data signal of in_words_1
-- bit 31~0 - in_words_1[31:0] (Read/Write)
-- 0x1c : reserved
-- 0x20 : Data signal of in_words_2
-- bit 31~0 - in_words_2[31:0] (Read/Write)
-- 0x24 : reserved
-- 0x28 : Data signal of in_words_3
-- bit 31~0 - in_words_3[31:0] (Read/Write)
-- 0x2c : reserved
-- 0x30 : Data signal of out_words_0
-- bit 31~0 - out_words_0[31:0] (Read)
-- 0x34 : Control signal of out_words_0
-- bit 0 - out_words_0_ap_vld (Read/COR)
-- others - reserved
-- 0x40 : Data signal of out_words_1
-- bit 31~0 - out_words_1[31:0] (Read)
-- 0x44 : Control signal of out_words_1
-- bit 0 - out_words_1_ap_vld (Read/COR)
-- others - reserved
-- 0x50 : Data signal of out_words_2
-- bit 31~0 - out_words_2[31:0] (Read)
-- 0x54 : Control signal of out_words_2
-- bit 0 - out_words_2_ap_vld (Read/COR)
-- others - reserved
-- 0x60 : Data signal of out_words_3
-- bit 31~0 - out_words_3[31:0] (Read)
-- 0x64 : Control signal of out_words_3
-- bit 0 - out_words_3_ap_vld (Read/COR)
-- others - reserved
-- (SC = Self Clear, COR = Clear on Read, TOW = Toggle on Write, COH = Clear on Handshake)
architecture behave of game_of_life_step_AXILiteS_s_axi is
type states is (wridle, wrdata, wrresp, wrreset, rdidle, rddata, rdreset); -- read and write fsm states
signal wstate : states := wrreset;
signal rstate : states := rdreset;
signal wnext, rnext: states;
constant ADDR_AP_CTRL : INTEGER := 16#00#;
constant ADDR_GIE : INTEGER := 16#04#;
constant ADDR_IER : INTEGER := 16#08#;
constant ADDR_ISR : INTEGER := 16#0c#;
constant ADDR_IN_WORDS_0_DATA_0 : INTEGER := 16#10#;
constant ADDR_IN_WORDS_0_CTRL : INTEGER := 16#14#;
constant ADDR_IN_WORDS_1_DATA_0 : INTEGER := 16#18#;
constant ADDR_IN_WORDS_1_CTRL : INTEGER := 16#1c#;
constant ADDR_IN_WORDS_2_DATA_0 : INTEGER := 16#20#;
constant ADDR_IN_WORDS_2_CTRL : INTEGER := 16#24#;
constant ADDR_IN_WORDS_3_DATA_0 : INTEGER := 16#28#;
constant ADDR_IN_WORDS_3_CTRL : INTEGER := 16#2c#;
constant ADDR_OUT_WORDS_0_DATA_0 : INTEGER := 16#30#;
constant ADDR_OUT_WORDS_0_CTRL : INTEGER := 16#34#;
constant ADDR_OUT_WORDS_1_DATA_0 : INTEGER := 16#40#;
constant ADDR_OUT_WORDS_1_CTRL : INTEGER := 16#44#;
constant ADDR_OUT_WORDS_2_DATA_0 : INTEGER := 16#50#;
constant ADDR_OUT_WORDS_2_CTRL : INTEGER := 16#54#;
constant ADDR_OUT_WORDS_3_DATA_0 : INTEGER := 16#60#;
constant ADDR_OUT_WORDS_3_CTRL : INTEGER := 16#64#;
constant ADDR_BITS : INTEGER := 7;
signal AWREADY_t : STD_LOGIC;
signal WREADY_t : STD_LOGIC;
signal ARREADY_t : STD_LOGIC;
signal RVALID_t : STD_LOGIC;
signal BVALID_t : STD_LOGIC;
signal waddr : UNSIGNED(ADDR_BITS-1 downto 0);
signal wmask : UNSIGNED(C_S_AXI_DATA_WIDTH-1 downto 0);
signal aw_hs : STD_LOGIC;
signal w_hs : STD_LOGIC;
signal rdata_data : UNSIGNED(C_S_AXI_DATA_WIDTH-1 downto 0);
signal ar_hs : STD_LOGIC;
signal raddr : UNSIGNED(ADDR_BITS-1 downto 0);
-- internal registers
signal int_ap_idle : STD_LOGIC := '0';
signal int_ap_ready : STD_LOGIC := '0';
signal task_ap_ready : STD_LOGIC;
signal int_ap_done : STD_LOGIC := '0';
signal task_ap_done : STD_LOGIC;
signal int_task_ap_done : STD_LOGIC := '0';
signal int_ap_start : STD_LOGIC := '0';
signal int_interrupt : STD_LOGIC := '0';
signal int_auto_restart : STD_LOGIC := '0';
signal auto_restart_status : STD_LOGIC := '0';
signal auto_restart_done : STD_LOGIC;
signal int_gie : STD_LOGIC := '0';
signal int_ier : UNSIGNED(1 downto 0) := (others => '0');
signal int_isr : UNSIGNED(1 downto 0) := (others => '0');
signal int_in_words_0 : UNSIGNED(31 downto 0) := (others => '0');
signal int_in_words_1 : UNSIGNED(31 downto 0) := (others => '0');
signal int_in_words_2 : UNSIGNED(31 downto 0) := (others => '0');
signal int_in_words_3 : UNSIGNED(31 downto 0) := (others => '0');
signal int_out_words_0_ap_vld : STD_LOGIC;
signal int_out_words_0 : UNSIGNED(31 downto 0) := (others => '0');
signal int_out_words_1_ap_vld : STD_LOGIC;
signal int_out_words_1 : UNSIGNED(31 downto 0) := (others => '0');
signal int_out_words_2_ap_vld : STD_LOGIC;
signal int_out_words_2 : UNSIGNED(31 downto 0) := (others => '0');
signal int_out_words_3_ap_vld : STD_LOGIC;
signal int_out_words_3 : UNSIGNED(31 downto 0) := (others => '0');
begin
-- ----------------------- Instantiation------------------
-- ----------------------- AXI WRITE ---------------------
AWREADY_t <= '1' when wstate = wridle else '0';
AWREADY <= AWREADY_t;
WREADY_t <= '1' when wstate = wrdata else '0';
WREADY <= WREADY_t;
BVALID_t <= '1' when wstate = wrresp else '0';
BVALID <= BVALID_t;
BRESP <= "00"; -- OKAY
wmask <= (31 downto 24 => WSTRB(3), 23 downto 16 => WSTRB(2), 15 downto 8 => WSTRB(1), 7 downto 0 => WSTRB(0));
aw_hs <= AWVALID and AWREADY_t;
w_hs <= WVALID and WREADY_t;
-- write FSM
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
wstate <= wrreset;
elsif (ACLK_EN = '1') then
wstate <= wnext;
end if;
end if;
end process;
process (wstate, AWVALID, WVALID, BREADY, BVALID_t)
begin
case (wstate) is
when wridle =>
if (AWVALID = '1') then
wnext <= wrdata;
else
wnext <= wridle;
end if;
when wrdata =>
if (WVALID = '1') then
wnext <= wrresp;
else
wnext <= wrdata;
end if;
when wrresp =>
if (BREADY = '1' and BVALID_t = '1') then
wnext <= wridle;
else
wnext <= wrresp;
end if;
when others =>
wnext <= wridle;
end case;
end process;
waddr_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ACLK_EN = '1') then
if (aw_hs = '1') then
waddr <= UNSIGNED(AWADDR(ADDR_BITS-1 downto 2) & (1 downto 0 => '0'));
end if;
end if;
end if;
end process;
-- ----------------------- AXI READ ----------------------
ARREADY_t <= '1' when (rstate = rdidle) else '0';
ARREADY <= ARREADY_t;
RDATA <= STD_LOGIC_VECTOR(rdata_data);
RRESP <= "00"; -- OKAY
RVALID_t <= '1' when (rstate = rddata) else '0';
RVALID <= RVALID_t;
ar_hs <= ARVALID and ARREADY_t;
raddr <= UNSIGNED(ARADDR(ADDR_BITS-1 downto 0));
-- read FSM
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
rstate <= rdreset;
elsif (ACLK_EN = '1') then
rstate <= rnext;
end if;
end if;
end process;
process (rstate, ARVALID, RREADY, RVALID_t)
begin
case (rstate) is
when rdidle =>
if (ARVALID = '1') then
rnext <= rddata;
else
rnext <= rdidle;
end if;
when rddata =>
if (RREADY = '1' and RVALID_t = '1') then
rnext <= rdidle;
else
rnext <= rddata;
end if;
when others =>
rnext <= rdidle;
end case;
end process;
rdata_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ACLK_EN = '1') then
if (ar_hs = '1') then
rdata_data <= (others => '0');
case (TO_INTEGER(raddr)) is
when ADDR_AP_CTRL =>
rdata_data(9) <= int_interrupt;
rdata_data(7) <= int_auto_restart;
rdata_data(3) <= int_ap_ready;
rdata_data(2) <= int_ap_idle;
rdata_data(1) <= int_task_ap_done;
rdata_data(0) <= int_ap_start;
when ADDR_GIE =>
rdata_data(0) <= int_gie;
when ADDR_IER =>
rdata_data(1 downto 0) <= int_ier;
when ADDR_ISR =>
rdata_data(1 downto 0) <= int_isr;
when ADDR_IN_WORDS_0_DATA_0 =>
rdata_data <= RESIZE(int_in_words_0(31 downto 0), 32);
when ADDR_IN_WORDS_1_DATA_0 =>
rdata_data <= RESIZE(int_in_words_1(31 downto 0), 32);
when ADDR_IN_WORDS_2_DATA_0 =>
rdata_data <= RESIZE(int_in_words_2(31 downto 0), 32);
when ADDR_IN_WORDS_3_DATA_0 =>
rdata_data <= RESIZE(int_in_words_3(31 downto 0), 32);
when ADDR_OUT_WORDS_0_DATA_0 =>
rdata_data <= RESIZE(int_out_words_0(31 downto 0), 32);
when ADDR_OUT_WORDS_0_CTRL =>
rdata_data(0) <= int_out_words_0_ap_vld;
when ADDR_OUT_WORDS_1_DATA_0 =>
rdata_data <= RESIZE(int_out_words_1(31 downto 0), 32);
when ADDR_OUT_WORDS_1_CTRL =>
rdata_data(0) <= int_out_words_1_ap_vld;
when ADDR_OUT_WORDS_2_DATA_0 =>
rdata_data <= RESIZE(int_out_words_2(31 downto 0), 32);
when ADDR_OUT_WORDS_2_CTRL =>
rdata_data(0) <= int_out_words_2_ap_vld;
when ADDR_OUT_WORDS_3_DATA_0 =>
rdata_data <= RESIZE(int_out_words_3(31 downto 0), 32);
when ADDR_OUT_WORDS_3_CTRL =>
rdata_data(0) <= int_out_words_3_ap_vld;
when others =>
NULL;
end case;
end if;
end if;
end if;
end process;
-- ----------------------- Register logic ----------------
interrupt <= int_interrupt;
ap_start <= int_ap_start;
task_ap_done <= (ap_done and not auto_restart_status) or auto_restart_done;
task_ap_ready <= ap_ready and not int_auto_restart;
auto_restart_done <= auto_restart_status and (ap_idle and not int_ap_idle);
in_words_0 <= STD_LOGIC_VECTOR(int_in_words_0);
in_words_1 <= STD_LOGIC_VECTOR(int_in_words_1);
in_words_2 <= STD_LOGIC_VECTOR(int_in_words_2);
in_words_3 <= STD_LOGIC_VECTOR(int_in_words_3);
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_interrupt <= '0';
elsif (ACLK_EN = '1') then
if (int_gie = '1' and (int_isr(0) or int_isr(1)) = '1') then
int_interrupt <= '1';
else
int_interrupt <= '0';
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_ap_start <= '0';
elsif (ACLK_EN = '1') then
if (w_hs = '1' and waddr = ADDR_AP_CTRL and WSTRB(0) = '1' and WDATA(0) = '1') then
int_ap_start <= '1';
elsif (ap_ready = '1') then
int_ap_start <= int_auto_restart; -- clear on handshake/auto restart
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_ap_done <= '0';
elsif (ACLK_EN = '1') then
if (true) then
int_ap_done <= ap_done;
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_task_ap_done <= '0';
elsif (ACLK_EN = '1') then
if (task_ap_done = '1') then
int_task_ap_done <= '1';
elsif (ar_hs = '1' and raddr = ADDR_AP_CTRL) then
int_task_ap_done <= '0'; -- clear on read
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_ap_idle <= '0';
elsif (ACLK_EN = '1') then
if (true) then
int_ap_idle <= ap_idle;
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_ap_ready <= '0';
elsif (ACLK_EN = '1') then
if (task_ap_ready = '1') then
int_ap_ready <= '1';
elsif (ar_hs = '1' and raddr = ADDR_AP_CTRL) then
int_ap_ready <= '0';
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_auto_restart <= '0';
elsif (ACLK_EN = '1') then
if (w_hs = '1' and waddr = ADDR_AP_CTRL and WSTRB(0) = '1') then
int_auto_restart <= WDATA(7);
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
auto_restart_status <= '0';
elsif (ACLK_EN = '1') then
if (int_auto_restart = '1') then
auto_restart_status <= '1';
elsif (ap_idle = '1') then
auto_restart_status <= '0';
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_gie <= '0';
elsif (ACLK_EN = '1') then
if (w_hs = '1' and waddr = ADDR_GIE and WSTRB(0) = '1') then
int_gie <= WDATA(0);
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_ier <= (others=>'0');
elsif (ACLK_EN = '1') then
if (w_hs = '1' and waddr = ADDR_IER and WSTRB(0) = '1') then
int_ier <= UNSIGNED(WDATA(1 downto 0));
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_isr(0) <= '0';
elsif (ACLK_EN = '1') then
if (int_ier(0) = '1' and ap_done = '1') then
int_isr(0) <= '1';
elsif (w_hs = '1' and waddr = ADDR_ISR and WSTRB(0) = '1') then
int_isr(0) <= int_isr(0) xor WDATA(0); -- toggle on write
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_isr(1) <= '0';
elsif (ACLK_EN = '1') then
if (int_ier(1) = '1' and ap_ready = '1') then
int_isr(1) <= '1';
elsif (w_hs = '1' and waddr = ADDR_ISR and WSTRB(0) = '1') then
int_isr(1) <= int_isr(1) xor WDATA(1); -- toggle on write
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_in_words_0(31 downto 0) <= (others => '0');
elsif (ACLK_EN = '1') then
if (w_hs = '1' and waddr = ADDR_IN_WORDS_0_DATA_0) then
int_in_words_0(31 downto 0) <= (UNSIGNED(WDATA(31 downto 0)) and wmask(31 downto 0)) or ((not wmask(31 downto 0)) and int_in_words_0(31 downto 0));
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_in_words_1(31 downto 0) <= (others => '0');
elsif (ACLK_EN = '1') then
if (w_hs = '1' and waddr = ADDR_IN_WORDS_1_DATA_0) then
int_in_words_1(31 downto 0) <= (UNSIGNED(WDATA(31 downto 0)) and wmask(31 downto 0)) or ((not wmask(31 downto 0)) and int_in_words_1(31 downto 0));
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_in_words_2(31 downto 0) <= (others => '0');
elsif (ACLK_EN = '1') then
if (w_hs = '1' and waddr = ADDR_IN_WORDS_2_DATA_0) then
int_in_words_2(31 downto 0) <= (UNSIGNED(WDATA(31 downto 0)) and wmask(31 downto 0)) or ((not wmask(31 downto 0)) and int_in_words_2(31 downto 0));
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_in_words_3(31 downto 0) <= (others => '0');
elsif (ACLK_EN = '1') then
if (w_hs = '1' and waddr = ADDR_IN_WORDS_3_DATA_0) then
int_in_words_3(31 downto 0) <= (UNSIGNED(WDATA(31 downto 0)) and wmask(31 downto 0)) or ((not wmask(31 downto 0)) and int_in_words_3(31 downto 0));
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_out_words_0 <= (others => '0');
elsif (ACLK_EN = '1') then
if (out_words_0_ap_vld = '1') then
int_out_words_0 <= UNSIGNED(out_words_0);
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_out_words_0_ap_vld <= '0';
elsif (ACLK_EN = '1') then
if (out_words_0_ap_vld = '1') then
int_out_words_0_ap_vld <= '1';
elsif (ar_hs = '1' and raddr = ADDR_OUT_WORDS_0_CTRL) then
int_out_words_0_ap_vld <= '0'; -- clear on read
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_out_words_1 <= (others => '0');
elsif (ACLK_EN = '1') then
if (out_words_1_ap_vld = '1') then
int_out_words_1 <= UNSIGNED(out_words_1);
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_out_words_1_ap_vld <= '0';
elsif (ACLK_EN = '1') then
if (out_words_1_ap_vld = '1') then
int_out_words_1_ap_vld <= '1';
elsif (ar_hs = '1' and raddr = ADDR_OUT_WORDS_1_CTRL) then
int_out_words_1_ap_vld <= '0'; -- clear on read
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_out_words_2 <= (others => '0');
elsif (ACLK_EN = '1') then
if (out_words_2_ap_vld = '1') then
int_out_words_2 <= UNSIGNED(out_words_2);
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_out_words_2_ap_vld <= '0';
elsif (ACLK_EN = '1') then
if (out_words_2_ap_vld = '1') then
int_out_words_2_ap_vld <= '1';
elsif (ar_hs = '1' and raddr = ADDR_OUT_WORDS_2_CTRL) then
int_out_words_2_ap_vld <= '0'; -- clear on read
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_out_words_3 <= (others => '0');
elsif (ACLK_EN = '1') then
if (out_words_3_ap_vld = '1') then
int_out_words_3 <= UNSIGNED(out_words_3);
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_out_words_3_ap_vld <= '0';
elsif (ACLK_EN = '1') then
if (out_words_3_ap_vld = '1') then
int_out_words_3_ap_vld <= '1';
elsif (ar_hs = '1' and raddr = ADDR_OUT_WORDS_3_CTRL) then
int_out_words_3_ap_vld <= '0'; -- clear on read
end if;
end if;
end if;
end process;
-- ----------------------- Memory logic ------------------
end architecture behave;

27
Practicals/practical-3b/game_of_life_practical3b/game_of_life_practical3b/hls/.autopilot/db/cosimDB.tcl Normal file
View File

@@ -0,0 +1,27 @@
set RtlHierarchyInfo {[
{"ID" : "0", "Level" : "0", "Path" : "`AUTOTB_DUT_INST", "Parent" : "", "Child" : ["1"],
"CDFG" : "game_of_life_step",
"Protocol" : "ap_ctrl_hs",
"ControlExist" : "1", "ap_start" : "1", "ap_ready" : "1", "ap_done" : "1", "ap_continue" : "0", "ap_idle" : "1", "real_start" : "0",
"Pipeline" : "None", "UnalignedPipeline" : "0", "RewindPipeline" : "0", "ProcessNetwork" : "0",
"II" : "0",
"VariableLatency" : "1", "ExactLatency" : "-1", "EstimateLatencyMin" : "1", "EstimateLatencyMax" : "1",
"Combinational" : "0",
"Datapath" : "0",
"ClockEnable" : "0",
"HasSubDataflow" : "0",
"InDataflowNetwork" : "0",
"HasNonBlockingOperation" : "0",
"IsBlackBox" : "0",
"Port" : [
{"Name" : "in_words_0", "Type" : "None", "Direction" : "I"},
{"Name" : "in_words_1", "Type" : "None", "Direction" : "I"},
{"Name" : "in_words_2", "Type" : "None", "Direction" : "I"},
{"Name" : "in_words_3", "Type" : "None", "Direction" : "I"},
{"Name" : "out_words_0", "Type" : "Vld", "Direction" : "O"},
{"Name" : "out_words_1", "Type" : "Vld", "Direction" : "O"},
{"Name" : "out_words_2", "Type" : "Vld", "Direction" : "O"},
{"Name" : "out_words_3", "Type" : "Vld", "Direction" : "O"}]},
{"ID" : "1", "Level" : "1", "Path" : "`AUTOTB_DUT_INST.AXILiteS_s_axi_U", "Parent" : "0"}]}

961
Practicals/practical-3b/game_of_life_practical3b/game_of_life_practical3b/hls/.autopilot/db/design.bindinfo.xml Normal file
View File

@@ -0,0 +1,961 @@
<?xml version="1.0" encoding="utf-8"?>
<BindInfo>
<BindNode BINDTYPE="op" DISPLAY="bind_op add" ID="" IMPL="fabric" LATENCY="0" OPTYPE="add" PRAGMA="" RTLNAME="add_ln69_fu_998_p2" SOURCE="gameoflife.cpp:69" VARIABLE="add_ln69" MODULE="game_of_life_step" LOOP="" BUNDLEDNAME="" DSP="0" BRAM="0" URAM="0" USAGE="" STORAGESUBTYPE="" STORAGESIZE=""/>
<BindNode BINDTYPE="op" DISPLAY="bind_op add" ID="" IMPL="fabric" LATENCY="0" OPTYPE="add" PRAGMA="" RTLNAME="add_ln69_1_fu_1008_p2" SOURCE="gameoflife.cpp:69" VARIABLE="add_ln69_1" MODULE="game_of_life_step" LOOP="" BUNDLEDNAME="" DSP="0" BRAM="0" URAM="0" USAGE="" STORAGESUBTYPE="" STORAGESIZE=""/>
<BindNode BINDTYPE="op" DISPLAY="bind_op add" ID="" IMPL="fabric" LATENCY="0" OPTYPE="add" PRAGMA="" RTLNAME="add_ln69_2_fu_1018_p2" SOURCE="gameoflife.cpp:69" VARIABLE="add_ln69_2" MODULE="game_of_life_step" LOOP="" BUNDLEDNAME="" DSP="0" BRAM="0" URAM="0" USAGE="" STORAGESUBTYPE="" STORAGESIZE=""/>
<BindNode BINDTYPE="op" DISPLAY="bind_op add" ID="" IMPL="fabric" LATENCY="0" OPTYPE="add" PRAGMA="" RTLNAME="add_ln69_3_fu_1028_p2" SOURCE="gameoflife.cpp:69" VARIABLE="add_ln69_3" MODULE="game_of_life_step" LOOP="" BUNDLEDNAME="" DSP="0" BRAM="0" URAM="0" USAGE="" STORAGESUBTYPE="" STORAGESIZE=""/>
<BindNode BINDTYPE="op" DISPLAY="bind_op add" ID="" IMPL="fabric" LATENCY="0" OPTYPE="add" PRAGMA="" RTLNAME="add_ln69_4_fu_1038_p2" SOURCE="gameoflife.cpp:69" VARIABLE="add_ln69_4" MODULE="game_of_life_step" LOOP="" BUNDLEDNAME="" DSP="0" BRAM="0" URAM="0" USAGE="" STORAGESUBTYPE="" STORAGESIZE=""/>
<BindNode BINDTYPE="op" DISPLAY="bind_op add" ID="" IMPL="fabric" LATENCY="0" OPTYPE="add" PRAGMA="" RTLNAME="add_ln69_5_fu_1048_p2" SOURCE="gameoflife.cpp:69" VARIABLE="add_ln69_5" MODULE="game_of_life_step" LOOP="" BUNDLEDNAME="" DSP="0" BRAM="0" URAM="0" USAGE="" STORAGESUBTYPE="" STORAGESIZE=""/>
<BindNode BINDTYPE="op" DISPLAY="bind_op add" ID="" IMPL="fabric" LATENCY="0" OPTYPE="add" PRAGMA="" RTLNAME="alive_neighbours_fu_1058_p2" SOURCE="gameoflife.cpp:69" VARIABLE="alive_neighbours" MODULE="game_of_life_step" LOOP="" BUNDLEDNAME="" DSP="0" BRAM="0" URAM="0" USAGE="" STORAGESUBTYPE="" STORAGESIZE=""/>
<BindNode BINDTYPE="op" DISPLAY="bind_op seteq" ID="" IMPL="auto" LATENCY="0" OPTYPE="seteq" PRAGMA="" RTLNAME="icmp_ln74_fu_6804_p2" SOURCE="gameoflife.cpp:74" VARIABLE="icmp_ln74" MODULE="game_of_life_step" LOOP="" BUNDLEDNAME="" DSP="0" BRAM="0" URAM="0" USAGE="" STORAGESUBTYPE="" STORAGESIZE=""/>
<BindNode BINDTYPE="op" DISPLAY="bind_op seteq" ID="" IMPL="auto" LATENCY="0" OPTYPE="seteq" PRAGMA="" RTLNAME="icmp_ln74_1_fu_6809_p2" SOURCE="gameoflife.cpp:74" VARIABLE="icmp_ln74_1" MODULE="game_of_life_step" LOOP="" BUNDLEDNAME="" DSP="0" BRAM="0" URAM="0" USAGE="" STORAGESUBTYPE="" STORAGESIZE=""/>
<BindNode BINDTYPE="op" DISPLAY="bind_op and" ID="" IMPL="auto" LATENCY="0" OPTYPE="and" PRAGMA="" RTLNAME="and_ln74_fu_6814_p2" SOURCE="gameoflife.cpp:74" VARIABLE="and_ln74" MODULE="game_of_life_step" LOOP="" BUNDLEDNAME="" DSP="0" BRAM="0" URAM="0" USAGE="" STORAGESUBTYPE="" STORAGESIZE=""/>
<BindNode BINDTYPE="op" DISPLAY="bind_op or" ID="" IMPL="auto" LATENCY="0" OPTYPE="or" PRAGMA="" RTLNAME="is_alive_after_step_fu_6819_p2" SOURCE="gameoflife.cpp:74" VARIABLE="is_alive_after_step" MODULE="game_of_life_step" LOOP="" BUNDLEDNAME="" DSP="0" BRAM="0" URAM="0" USAGE="" STORAGESUBTYPE="" STORAGESIZE=""/>
<BindNode BINDTYPE="op" DISPLAY="bind_op add" ID="" IMPL="fabric" LATENCY="0" OPTYPE="add" PRAGMA="" RTLNAME="add_ln69_7_fu_1080_p2" SOURCE="gameoflife.cpp:69" VARIABLE="add_ln69_7" MODULE="game_of_life_step" LOOP="" BUNDLEDNAME="" DSP="0" BRAM="0" URAM="0" USAGE="" STORAGESUBTYPE="" STORAGESIZE=""/>
<BindNode BINDTYPE="op" DISPLAY="bind_op add" ID="" IMPL="fabric" LATENCY="0" OPTYPE="add" PRAGMA="" RTLNAME="add_ln69_8_fu_1090_p2" SOURCE="gameoflife.cpp:69" VARIABLE="add_ln69_8" MODULE="game_of_life_step" LOOP="" BUNDLEDNAME="" DSP="0" BRAM="0" URAM="0" USAGE="" STORAGESUBTYPE="" STORAGESIZE=""/>
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<BindNode BINDTYPE="op" DISPLAY="bind_op add" ID="" IMPL="fabric" LATENCY="0" OPTYPE="add" PRAGMA="" RTLNAME="alive_neighbours_113_fu_6798_p2" SOURCE="gameoflife.cpp:69" VARIABLE="alive_neighbours_113" MODULE="game_of_life_step" LOOP="" BUNDLEDNAME="" DSP="0" BRAM="0" URAM="0" USAGE="" STORAGESUBTYPE="" STORAGESIZE=""/>
<BindNode BINDTYPE="op" DISPLAY="bind_op seteq" ID="" IMPL="auto" LATENCY="0" OPTYPE="seteq" PRAGMA="" RTLNAME="icmp_ln74_198_fu_8934_p2" SOURCE="gameoflife.cpp:74" VARIABLE="icmp_ln74_198" MODULE="game_of_life_step" LOOP="" BUNDLEDNAME="" DSP="0" BRAM="0" URAM="0" USAGE="" STORAGESUBTYPE="" STORAGESIZE=""/>
<BindNode BINDTYPE="op" DISPLAY="bind_op seteq" ID="" IMPL="auto" LATENCY="0" OPTYPE="seteq" PRAGMA="" RTLNAME="icmp_ln74_199_fu_8939_p2" SOURCE="gameoflife.cpp:74" VARIABLE="icmp_ln74_199" MODULE="game_of_life_step" LOOP="" BUNDLEDNAME="" DSP="0" BRAM="0" URAM="0" USAGE="" STORAGESUBTYPE="" STORAGESIZE=""/>
<BindNode BINDTYPE="op" DISPLAY="bind_op and" ID="" IMPL="auto" LATENCY="0" OPTYPE="and" PRAGMA="" RTLNAME="and_ln74_99_fu_8944_p2" SOURCE="gameoflife.cpp:74" VARIABLE="and_ln74_99" MODULE="game_of_life_step" LOOP="" BUNDLEDNAME="" DSP="0" BRAM="0" URAM="0" USAGE="" STORAGESUBTYPE="" STORAGESIZE=""/>
<BindNode BINDTYPE="op" DISPLAY="bind_op or" ID="" IMPL="auto" LATENCY="0" OPTYPE="or" PRAGMA="" RTLNAME="is_alive_after_step_99_fu_8949_p2" SOURCE="gameoflife.cpp:74" VARIABLE="is_alive_after_step_99" MODULE="game_of_life_step" LOOP="" BUNDLEDNAME="" DSP="0" BRAM="0" URAM="0" USAGE="" STORAGESUBTYPE="" STORAGESIZE=""/>
<BindNode BINDTYPE="adapter" DISPLAY="bind_adapter axilite" ID="" IMPL="" LATENCY="" OPTYPE="" PRAGMA="" RTLNAME="AXILiteS_s_axi_U" SOURCE="" VARIABLE="" MODULE="game_of_life_step" LOOP="" BUNDLEDNAME="AXILiteS" DSP="0" BRAM="0" URAM="0" USAGE="interface" STORAGESUBTYPE="s_axilite" STORAGESIZE=""/>
</BindInfo>

19
Practicals/practical-3b/game_of_life_practical3b/game_of_life_practical3b/hls/.autopilot/db/driver/data/game_of_life_step.mdd Normal file
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# ==============================================================
# Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2025.1 (64-bit)
# Tool Version Limit: 2025.05
# Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
# Copyright 2022-2025 Advanced Micro Devices, Inc. All Rights Reserved.
#
# ==============================================================
OPTION psf_version = 2.1;
BEGIN driver game_of_life_step
OPTION supported_peripherals = (game_of_life_step_v1_0 );
OPTION driver_state = ACTIVE;
OPTION copyfiles = all;
OPTION name = game_of_life_step;
OPTION version = 1.0;
END driver

24
Practicals/practical-3b/game_of_life_practical3b/game_of_life_practical3b/hls/.autopilot/db/driver/data/game_of_life_step.tcl Normal file
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# ==============================================================
# Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2025.1 (64-bit)
# Tool Version Limit: 2025.05
# Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
# Copyright 2022-2025 Advanced Micro Devices, Inc. All Rights Reserved.
#
# ==============================================================
proc generate {drv_handle} {
xdefine_include_file $drv_handle "xparameters.h" "XGame_of_life_step" \
"NUM_INSTANCES" \
"DEVICE_ID" \
"C_S_AXI_AXILITES_BASEADDR" \
"C_S_AXI_AXILITES_HIGHADDR"
xdefine_config_file $drv_handle "xgame_of_life_step_g.c" "XGame_of_life_step" \
"DEVICE_ID" \
"C_S_AXI_AXILITES_BASEADDR"
xdefine_canonical_xpars $drv_handle "xparameters.h" "XGame_of_life_step" \
"DEVICE_ID" \
"C_S_AXI_AXILITES_BASEADDR" \
"C_S_AXI_AXILITES_HIGHADDR"
}

24
Practicals/practical-3b/game_of_life_practical3b/game_of_life_practical3b/hls/.autopilot/db/driver/data/game_of_life_step.yaml Normal file
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# ==============================================================
# Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2025.1 (64-bit)
# Tool Version Limit: 2025.05
# Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
# Copyright 2022-2025 Advanced Micro Devices, Inc. All Rights Reserved.
#
# ==============================================================
%YAML 1.2
---
title: game_of_life_step driver
type: driver
properties:
compatible:
items:
- const: xlnx,game-of-life-step-1.0
config:
- XGame_of_life_step_Config
required:
- compatible
- reg
additionalProperties:
- interrupts
- interrupt-parent

25
Practicals/practical-3b/game_of_life_practical3b/game_of_life_practical3b/hls/.autopilot/db/driver/src/CMakeLists.txt Normal file
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# ==============================================================
# Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2025.1 (64-bit)
# Tool Version Limit: 2025.05
# Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
# Copyright 2022-2025 Advanced Micro Devices, Inc. All Rights Reserved.
#
# ==============================================================
cmake_minimum_required(VERSION 3.15)
project(game_of_life_step)
find_package(common)
collector_create (PROJECT_LIB_SOURCES "${CMAKE_CURRENT_SOURCE_DIR}")
collect (PROJECT_LIB_SOURCES xgame_of_life_step.c)
collect (PROJECT_LIB_SOURCES xgame_of_life_step_sinit.c)
collect (PROJECT_LIB_SOURCES xgame_of_life_step_linux.c)
collect (PROJECT_LIB_SOURCES xgame_of_life_step_g.c)
collector_list (_sources PROJECT_LIB_SOURCES)
collector_create (PROJECT_LIB_HEADERS "${CMAKE_CURRENT_SOURCE_DIR}")
collect (PROJECT_LIB_HEADERS xgame_of_life_step.h)
collect (PROJECT_LIB_HEADERS xgame_of_life_step_hw.h)
collector_list (_headers PROJECT_LIB_HEADERS)
file(COPY ${_headers} DESTINATION ${CMAKE_BINARY_DIR}/include)
include_directories(${CMAKE_BINARY_DIR}/include)
add_library(game_of_life_step STATIC ${_sources})
set_target_properties(game_of_life_step PROPERTIES LINKER_LANGUAGE C)

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# ==============================================================
# Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2025.1 (64-bit)
# Tool Version Limit: 2025.05
# Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
# Copyright 2022-2025 Advanced Micro Devices, Inc. All Rights Reserved.
#
# ==============================================================
COMPILER=
ARCHIVER=
CP=cp
RM=rm
COMPILER_FLAGS=
EXTRA_COMPILER_FLAGS=
ARCHIVER_FLAGS=
CORENAME=game_of_life_step
RELEASEDIR=../../../lib
OBJDIR=$(RELEASEDIR)
LIBDIR=$(RELEASEDIR)
INCLUDEDIR=../../../include
INCLUDES=-I./. -I$(INCLUDEDIR)
# Source files
SRCS := $(wildcard *.c)
HEADERS := $(wildcard *.h)
# Generated files
LIB := $(LIBDIR)/libxil.a
OBJS := $(addprefix $(OBJDIR)/,$(addsuffix .o,$(basename $(SRCS))))
RELEASE_HEADERS := $(addprefix $(INCLUDEDIR)/,$(notdir $(HEADERS)))
# Rules to compile and link
$(OBJDIR)/%.o: %.c
$(COMPILER) $(COMPILER_FLAGS) $(EXTRA_COMPILER_FLAGS) $(INCLUDES) -o $@ $<
$(LIB): $(OBJS)
$(ARCHIVER) $(ARCHIVER_FLAGS) -r $@ $^
# Rule to release include files
$(INCLUDEDIR)/%.h: %.h
$(CP) $< $@
# Dependencies between sources and objects
$(OBJS): $(SRCS) | $(HEADERS)
# Named targets for use by others
include: $(RELEASE_HEADERS)
includes: include
libs: $(LIB) banner
objs: $(OBJS)
# Helper targets
clean:
$(RM) -f $(LIB) $(OBJS) $(RELEASE_HEADERS)
banner:
echo "Building $(CORENAME)"
.PHONY: clean include objs libs includes banner

281
Practicals/practical-3b/game_of_life_practical3b/game_of_life_practical3b/hls/.autopilot/db/driver/src/xgame_of_life_step.c Normal file
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// ==============================================================
// Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2025.1 (64-bit)
// Tool Version Limit: 2025.05
// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
// Copyright 2022-2025 Advanced Micro Devices, Inc. All Rights Reserved.
//
// ==============================================================
/***************************** Include Files *********************************/
#include "xgame_of_life_step.h"
/************************** Function Implementation *************************/
#ifndef __linux__
int XGame_of_life_step_CfgInitialize(XGame_of_life_step *InstancePtr, XGame_of_life_step_Config *ConfigPtr) {
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(ConfigPtr != NULL);
InstancePtr->Axilites_BaseAddress = ConfigPtr->Axilites_BaseAddress;
InstancePtr->IsReady = XIL_COMPONENT_IS_READY;
return XST_SUCCESS;
}
#endif
void XGame_of_life_step_Start(XGame_of_life_step *InstancePtr) {
u32 Data;
Xil_AssertVoid(InstancePtr != NULL);
Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
Data = XGame_of_life_step_ReadReg(InstancePtr->Axilites_BaseAddress, XGAME_OF_LIFE_STEP_AXILITES_ADDR_AP_CTRL) & 0x80;
XGame_of_life_step_WriteReg(InstancePtr->Axilites_BaseAddress, XGAME_OF_LIFE_STEP_AXILITES_ADDR_AP_CTRL, Data | 0x01);
}
u32 XGame_of_life_step_IsDone(XGame_of_life_step *InstancePtr) {
u32 Data;
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
Data = XGame_of_life_step_ReadReg(InstancePtr->Axilites_BaseAddress, XGAME_OF_LIFE_STEP_AXILITES_ADDR_AP_CTRL);
return (Data >> 1) & 0x1;
}
u32 XGame_of_life_step_IsIdle(XGame_of_life_step *InstancePtr) {
u32 Data;
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
Data = XGame_of_life_step_ReadReg(InstancePtr->Axilites_BaseAddress, XGAME_OF_LIFE_STEP_AXILITES_ADDR_AP_CTRL);
return (Data >> 2) & 0x1;
}
u32 XGame_of_life_step_IsReady(XGame_of_life_step *InstancePtr) {
u32 Data;
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
Data = XGame_of_life_step_ReadReg(InstancePtr->Axilites_BaseAddress, XGAME_OF_LIFE_STEP_AXILITES_ADDR_AP_CTRL);
// check ap_start to see if the pcore is ready for next input
return !(Data & 0x1);
}
void XGame_of_life_step_EnableAutoRestart(XGame_of_life_step *InstancePtr) {
Xil_AssertVoid(InstancePtr != NULL);
Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
XGame_of_life_step_WriteReg(InstancePtr->Axilites_BaseAddress, XGAME_OF_LIFE_STEP_AXILITES_ADDR_AP_CTRL, 0x80);
}
void XGame_of_life_step_DisableAutoRestart(XGame_of_life_step *InstancePtr) {
Xil_AssertVoid(InstancePtr != NULL);
Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
XGame_of_life_step_WriteReg(InstancePtr->Axilites_BaseAddress, XGAME_OF_LIFE_STEP_AXILITES_ADDR_AP_CTRL, 0);
}
void XGame_of_life_step_Set_in_words_0(XGame_of_life_step *InstancePtr, u32 Data) {
Xil_AssertVoid(InstancePtr != NULL);
Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
XGame_of_life_step_WriteReg(InstancePtr->Axilites_BaseAddress, XGAME_OF_LIFE_STEP_AXILITES_ADDR_IN_WORDS_0_DATA, Data);
}
u32 XGame_of_life_step_Get_in_words_0(XGame_of_life_step *InstancePtr) {
u32 Data;
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
Data = XGame_of_life_step_ReadReg(InstancePtr->Axilites_BaseAddress, XGAME_OF_LIFE_STEP_AXILITES_ADDR_IN_WORDS_0_DATA);
return Data;
}
void XGame_of_life_step_Set_in_words_1(XGame_of_life_step *InstancePtr, u32 Data) {
Xil_AssertVoid(InstancePtr != NULL);
Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
XGame_of_life_step_WriteReg(InstancePtr->Axilites_BaseAddress, XGAME_OF_LIFE_STEP_AXILITES_ADDR_IN_WORDS_1_DATA, Data);
}
u32 XGame_of_life_step_Get_in_words_1(XGame_of_life_step *InstancePtr) {
u32 Data;
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
Data = XGame_of_life_step_ReadReg(InstancePtr->Axilites_BaseAddress, XGAME_OF_LIFE_STEP_AXILITES_ADDR_IN_WORDS_1_DATA);
return Data;
}
void XGame_of_life_step_Set_in_words_2(XGame_of_life_step *InstancePtr, u32 Data) {
Xil_AssertVoid(InstancePtr != NULL);
Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
XGame_of_life_step_WriteReg(InstancePtr->Axilites_BaseAddress, XGAME_OF_LIFE_STEP_AXILITES_ADDR_IN_WORDS_2_DATA, Data);
}
u32 XGame_of_life_step_Get_in_words_2(XGame_of_life_step *InstancePtr) {
u32 Data;
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
Data = XGame_of_life_step_ReadReg(InstancePtr->Axilites_BaseAddress, XGAME_OF_LIFE_STEP_AXILITES_ADDR_IN_WORDS_2_DATA);
return Data;
}
void XGame_of_life_step_Set_in_words_3(XGame_of_life_step *InstancePtr, u32 Data) {
Xil_AssertVoid(InstancePtr != NULL);
Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
XGame_of_life_step_WriteReg(InstancePtr->Axilites_BaseAddress, XGAME_OF_LIFE_STEP_AXILITES_ADDR_IN_WORDS_3_DATA, Data);
}
u32 XGame_of_life_step_Get_in_words_3(XGame_of_life_step *InstancePtr) {
u32 Data;
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
Data = XGame_of_life_step_ReadReg(InstancePtr->Axilites_BaseAddress, XGAME_OF_LIFE_STEP_AXILITES_ADDR_IN_WORDS_3_DATA);
return Data;
}
u32 XGame_of_life_step_Get_out_words_0(XGame_of_life_step *InstancePtr) {
u32 Data;
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
Data = XGame_of_life_step_ReadReg(InstancePtr->Axilites_BaseAddress, XGAME_OF_LIFE_STEP_AXILITES_ADDR_OUT_WORDS_0_DATA);
return Data;
}
u32 XGame_of_life_step_Get_out_words_0_vld(XGame_of_life_step *InstancePtr) {
u32 Data;
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
Data = XGame_of_life_step_ReadReg(InstancePtr->Axilites_BaseAddress, XGAME_OF_LIFE_STEP_AXILITES_ADDR_OUT_WORDS_0_CTRL);
return Data & 0x1;
}
u32 XGame_of_life_step_Get_out_words_1(XGame_of_life_step *InstancePtr) {
u32 Data;
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
Data = XGame_of_life_step_ReadReg(InstancePtr->Axilites_BaseAddress, XGAME_OF_LIFE_STEP_AXILITES_ADDR_OUT_WORDS_1_DATA);
return Data;
}
u32 XGame_of_life_step_Get_out_words_1_vld(XGame_of_life_step *InstancePtr) {
u32 Data;
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
Data = XGame_of_life_step_ReadReg(InstancePtr->Axilites_BaseAddress, XGAME_OF_LIFE_STEP_AXILITES_ADDR_OUT_WORDS_1_CTRL);
return Data & 0x1;
}
u32 XGame_of_life_step_Get_out_words_2(XGame_of_life_step *InstancePtr) {
u32 Data;
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
Data = XGame_of_life_step_ReadReg(InstancePtr->Axilites_BaseAddress, XGAME_OF_LIFE_STEP_AXILITES_ADDR_OUT_WORDS_2_DATA);
return Data;
}
u32 XGame_of_life_step_Get_out_words_2_vld(XGame_of_life_step *InstancePtr) {
u32 Data;
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
Data = XGame_of_life_step_ReadReg(InstancePtr->Axilites_BaseAddress, XGAME_OF_LIFE_STEP_AXILITES_ADDR_OUT_WORDS_2_CTRL);
return Data & 0x1;
}
u32 XGame_of_life_step_Get_out_words_3(XGame_of_life_step *InstancePtr) {
u32 Data;
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
Data = XGame_of_life_step_ReadReg(InstancePtr->Axilites_BaseAddress, XGAME_OF_LIFE_STEP_AXILITES_ADDR_OUT_WORDS_3_DATA);
return Data;
}
u32 XGame_of_life_step_Get_out_words_3_vld(XGame_of_life_step *InstancePtr) {
u32 Data;
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
Data = XGame_of_life_step_ReadReg(InstancePtr->Axilites_BaseAddress, XGAME_OF_LIFE_STEP_AXILITES_ADDR_OUT_WORDS_3_CTRL);
return Data & 0x1;
}
void XGame_of_life_step_InterruptGlobalEnable(XGame_of_life_step *InstancePtr) {
Xil_AssertVoid(InstancePtr != NULL);
Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
XGame_of_life_step_WriteReg(InstancePtr->Axilites_BaseAddress, XGAME_OF_LIFE_STEP_AXILITES_ADDR_GIE, 1);
}
void XGame_of_life_step_InterruptGlobalDisable(XGame_of_life_step *InstancePtr) {
Xil_AssertVoid(InstancePtr != NULL);
Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
XGame_of_life_step_WriteReg(InstancePtr->Axilites_BaseAddress, XGAME_OF_LIFE_STEP_AXILITES_ADDR_GIE, 0);
}
void XGame_of_life_step_InterruptEnable(XGame_of_life_step *InstancePtr, u32 Mask) {
u32 Register;
Xil_AssertVoid(InstancePtr != NULL);
Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
Register = XGame_of_life_step_ReadReg(InstancePtr->Axilites_BaseAddress, XGAME_OF_LIFE_STEP_AXILITES_ADDR_IER);
XGame_of_life_step_WriteReg(InstancePtr->Axilites_BaseAddress, XGAME_OF_LIFE_STEP_AXILITES_ADDR_IER, Register | Mask);
}
void XGame_of_life_step_InterruptDisable(XGame_of_life_step *InstancePtr, u32 Mask) {
u32 Register;
Xil_AssertVoid(InstancePtr != NULL);
Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
Register = XGame_of_life_step_ReadReg(InstancePtr->Axilites_BaseAddress, XGAME_OF_LIFE_STEP_AXILITES_ADDR_IER);
XGame_of_life_step_WriteReg(InstancePtr->Axilites_BaseAddress, XGAME_OF_LIFE_STEP_AXILITES_ADDR_IER, Register & (~Mask));
}
void XGame_of_life_step_InterruptClear(XGame_of_life_step *InstancePtr, u32 Mask) {
Xil_AssertVoid(InstancePtr != NULL);
Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
XGame_of_life_step_WriteReg(InstancePtr->Axilites_BaseAddress, XGAME_OF_LIFE_STEP_AXILITES_ADDR_ISR, Mask);
}
u32 XGame_of_life_step_InterruptGetEnabled(XGame_of_life_step *InstancePtr) {
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
return XGame_of_life_step_ReadReg(InstancePtr->Axilites_BaseAddress, XGAME_OF_LIFE_STEP_AXILITES_ADDR_IER);
}
u32 XGame_of_life_step_InterruptGetStatus(XGame_of_life_step *InstancePtr) {
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
return XGame_of_life_step_ReadReg(InstancePtr->Axilites_BaseAddress, XGAME_OF_LIFE_STEP_AXILITES_ADDR_ISR);
}

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// ==============================================================
// Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2025.1 (64-bit)
// Tool Version Limit: 2025.05
// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
// Copyright 2022-2025 Advanced Micro Devices, Inc. All Rights Reserved.
//
// ==============================================================
#ifndef XGAME_OF_LIFE_STEP_H
#define XGAME_OF_LIFE_STEP_H
#ifdef __cplusplus
extern "C" {
#endif
/***************************** Include Files *********************************/
#ifndef __linux__
#include "xil_types.h"
#include "xil_assert.h"
#include "xstatus.h"
#include "xil_io.h"
#else
#include <stdint.h>
#include <assert.h>
#include <dirent.h>
#include <fcntl.h>
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <sys/mman.h>
#include <unistd.h>
#include <stddef.h>
#endif
#include "xgame_of_life_step_hw.h"
/**************************** Type Definitions ******************************/
#ifdef __linux__
typedef uint8_t u8;
typedef uint16_t u16;
typedef uint32_t u32;
typedef uint64_t u64;
#else
typedef struct {
#ifdef SDT
char *Name;
#else
u16 DeviceId;
#endif
u64 Axilites_BaseAddress;
} XGame_of_life_step_Config;
#endif
typedef struct {
u64 Axilites_BaseAddress;
u32 IsReady;
} XGame_of_life_step;
typedef u32 word_type;
/***************** Macros (Inline Functions) Definitions *********************/
#ifndef __linux__
#define XGame_of_life_step_WriteReg(BaseAddress, RegOffset, Data) \
Xil_Out32((BaseAddress) + (RegOffset), (u32)(Data))
#define XGame_of_life_step_ReadReg(BaseAddress, RegOffset) \
Xil_In32((BaseAddress) + (RegOffset))
#else
#define XGame_of_life_step_WriteReg(BaseAddress, RegOffset, Data) \
*(volatile u32*)((BaseAddress) + (RegOffset)) = (u32)(Data)
#define XGame_of_life_step_ReadReg(BaseAddress, RegOffset) \
*(volatile u32*)((BaseAddress) + (RegOffset))
#define Xil_AssertVoid(expr) assert(expr)
#define Xil_AssertNonvoid(expr) assert(expr)
#define XST_SUCCESS 0
#define XST_DEVICE_NOT_FOUND 2
#define XST_OPEN_DEVICE_FAILED 3
#define XIL_COMPONENT_IS_READY 1
#endif
/************************** Function Prototypes *****************************/
#ifndef __linux__
#ifdef SDT
int XGame_of_life_step_Initialize(XGame_of_life_step *InstancePtr, UINTPTR BaseAddress);
XGame_of_life_step_Config* XGame_of_life_step_LookupConfig(UINTPTR BaseAddress);
#else
int XGame_of_life_step_Initialize(XGame_of_life_step *InstancePtr, u16 DeviceId);
XGame_of_life_step_Config* XGame_of_life_step_LookupConfig(u16 DeviceId);
#endif
int XGame_of_life_step_CfgInitialize(XGame_of_life_step *InstancePtr, XGame_of_life_step_Config *ConfigPtr);
#else
int XGame_of_life_step_Initialize(XGame_of_life_step *InstancePtr, const char* InstanceName);
int XGame_of_life_step_Release(XGame_of_life_step *InstancePtr);
#endif
void XGame_of_life_step_Start(XGame_of_life_step *InstancePtr);
u32 XGame_of_life_step_IsDone(XGame_of_life_step *InstancePtr);
u32 XGame_of_life_step_IsIdle(XGame_of_life_step *InstancePtr);
u32 XGame_of_life_step_IsReady(XGame_of_life_step *InstancePtr);
void XGame_of_life_step_EnableAutoRestart(XGame_of_life_step *InstancePtr);
void XGame_of_life_step_DisableAutoRestart(XGame_of_life_step *InstancePtr);
void XGame_of_life_step_Set_in_words_0(XGame_of_life_step *InstancePtr, u32 Data);
u32 XGame_of_life_step_Get_in_words_0(XGame_of_life_step *InstancePtr);
void XGame_of_life_step_Set_in_words_1(XGame_of_life_step *InstancePtr, u32 Data);
u32 XGame_of_life_step_Get_in_words_1(XGame_of_life_step *InstancePtr);
void XGame_of_life_step_Set_in_words_2(XGame_of_life_step *InstancePtr, u32 Data);
u32 XGame_of_life_step_Get_in_words_2(XGame_of_life_step *InstancePtr);
void XGame_of_life_step_Set_in_words_3(XGame_of_life_step *InstancePtr, u32 Data);
u32 XGame_of_life_step_Get_in_words_3(XGame_of_life_step *InstancePtr);
u32 XGame_of_life_step_Get_out_words_0(XGame_of_life_step *InstancePtr);
u32 XGame_of_life_step_Get_out_words_0_vld(XGame_of_life_step *InstancePtr);
u32 XGame_of_life_step_Get_out_words_1(XGame_of_life_step *InstancePtr);
u32 XGame_of_life_step_Get_out_words_1_vld(XGame_of_life_step *InstancePtr);
u32 XGame_of_life_step_Get_out_words_2(XGame_of_life_step *InstancePtr);
u32 XGame_of_life_step_Get_out_words_2_vld(XGame_of_life_step *InstancePtr);
u32 XGame_of_life_step_Get_out_words_3(XGame_of_life_step *InstancePtr);
u32 XGame_of_life_step_Get_out_words_3_vld(XGame_of_life_step *InstancePtr);
void XGame_of_life_step_InterruptGlobalEnable(XGame_of_life_step *InstancePtr);
void XGame_of_life_step_InterruptGlobalDisable(XGame_of_life_step *InstancePtr);
void XGame_of_life_step_InterruptEnable(XGame_of_life_step *InstancePtr, u32 Mask);
void XGame_of_life_step_InterruptDisable(XGame_of_life_step *InstancePtr, u32 Mask);
void XGame_of_life_step_InterruptClear(XGame_of_life_step *InstancePtr, u32 Mask);
u32 XGame_of_life_step_InterruptGetEnabled(XGame_of_life_step *InstancePtr);
u32 XGame_of_life_step_InterruptGetStatus(XGame_of_life_step *InstancePtr);
#ifdef __cplusplus
}
#endif
#endif

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Practicals/practical-3b/game_of_life_practical3b/game_of_life_practical3b/hls/.autopilot/db/driver/src/xgame_of_life_step_hw.h Normal file
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// ==============================================================
// Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2025.1 (64-bit)
// Tool Version Limit: 2025.05
// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
// Copyright 2022-2025 Advanced Micro Devices, Inc. All Rights Reserved.
//
// ==============================================================
// AXILiteS
// 0x00 : Control signals
// bit 0 - ap_start (Read/Write/COH)
// bit 1 - ap_done (Read/COR)
// bit 2 - ap_idle (Read)
// bit 3 - ap_ready (Read/COR)
// bit 7 - auto_restart (Read/Write)
// bit 9 - interrupt (Read)
// others - reserved
// 0x04 : Global Interrupt Enable Register
// bit 0 - Global Interrupt Enable (Read/Write)
// others - reserved
// 0x08 : IP Interrupt Enable Register (Read/Write)
// bit 0 - enable ap_done interrupt (Read/Write)
// bit 1 - enable ap_ready interrupt (Read/Write)
// others - reserved
// 0x0c : IP Interrupt Status Register (Read/TOW)
// bit 0 - ap_done (Read/TOW)
// bit 1 - ap_ready (Read/TOW)
// others - reserved
// 0x10 : Data signal of in_words_0
// bit 31~0 - in_words_0[31:0] (Read/Write)
// 0x14 : reserved
// 0x18 : Data signal of in_words_1
// bit 31~0 - in_words_1[31:0] (Read/Write)
// 0x1c : reserved
// 0x20 : Data signal of in_words_2
// bit 31~0 - in_words_2[31:0] (Read/Write)
// 0x24 : reserved
// 0x28 : Data signal of in_words_3
// bit 31~0 - in_words_3[31:0] (Read/Write)
// 0x2c : reserved
// 0x30 : Data signal of out_words_0
// bit 31~0 - out_words_0[31:0] (Read)
// 0x34 : Control signal of out_words_0
// bit 0 - out_words_0_ap_vld (Read/COR)
// others - reserved
// 0x40 : Data signal of out_words_1
// bit 31~0 - out_words_1[31:0] (Read)
// 0x44 : Control signal of out_words_1
// bit 0 - out_words_1_ap_vld (Read/COR)
// others - reserved
// 0x50 : Data signal of out_words_2
// bit 31~0 - out_words_2[31:0] (Read)
// 0x54 : Control signal of out_words_2
// bit 0 - out_words_2_ap_vld (Read/COR)
// others - reserved
// 0x60 : Data signal of out_words_3
// bit 31~0 - out_words_3[31:0] (Read)
// 0x64 : Control signal of out_words_3
// bit 0 - out_words_3_ap_vld (Read/COR)
// others - reserved
// (SC = Self Clear, COR = Clear on Read, TOW = Toggle on Write, COH = Clear on Handshake)
#define XGAME_OF_LIFE_STEP_AXILITES_ADDR_AP_CTRL 0x00
#define XGAME_OF_LIFE_STEP_AXILITES_ADDR_GIE 0x04
#define XGAME_OF_LIFE_STEP_AXILITES_ADDR_IER 0x08
#define XGAME_OF_LIFE_STEP_AXILITES_ADDR_ISR 0x0c
#define XGAME_OF_LIFE_STEP_AXILITES_ADDR_IN_WORDS_0_DATA 0x10
#define XGAME_OF_LIFE_STEP_AXILITES_BITS_IN_WORDS_0_DATA 32
#define XGAME_OF_LIFE_STEP_AXILITES_ADDR_IN_WORDS_1_DATA 0x18
#define XGAME_OF_LIFE_STEP_AXILITES_BITS_IN_WORDS_1_DATA 32
#define XGAME_OF_LIFE_STEP_AXILITES_ADDR_IN_WORDS_2_DATA 0x20
#define XGAME_OF_LIFE_STEP_AXILITES_BITS_IN_WORDS_2_DATA 32
#define XGAME_OF_LIFE_STEP_AXILITES_ADDR_IN_WORDS_3_DATA 0x28
#define XGAME_OF_LIFE_STEP_AXILITES_BITS_IN_WORDS_3_DATA 32
#define XGAME_OF_LIFE_STEP_AXILITES_ADDR_OUT_WORDS_0_DATA 0x30
#define XGAME_OF_LIFE_STEP_AXILITES_BITS_OUT_WORDS_0_DATA 32
#define XGAME_OF_LIFE_STEP_AXILITES_ADDR_OUT_WORDS_0_CTRL 0x34
#define XGAME_OF_LIFE_STEP_AXILITES_ADDR_OUT_WORDS_1_DATA 0x40
#define XGAME_OF_LIFE_STEP_AXILITES_BITS_OUT_WORDS_1_DATA 32
#define XGAME_OF_LIFE_STEP_AXILITES_ADDR_OUT_WORDS_1_CTRL 0x44
#define XGAME_OF_LIFE_STEP_AXILITES_ADDR_OUT_WORDS_2_DATA 0x50
#define XGAME_OF_LIFE_STEP_AXILITES_BITS_OUT_WORDS_2_DATA 32
#define XGAME_OF_LIFE_STEP_AXILITES_ADDR_OUT_WORDS_2_CTRL 0x54
#define XGAME_OF_LIFE_STEP_AXILITES_ADDR_OUT_WORDS_3_DATA 0x60
#define XGAME_OF_LIFE_STEP_AXILITES_BITS_OUT_WORDS_3_DATA 32
#define XGAME_OF_LIFE_STEP_AXILITES_ADDR_OUT_WORDS_3_CTRL 0x64

150
Practicals/practical-3b/game_of_life_practical3b/game_of_life_practical3b/hls/.autopilot/db/driver/src/xgame_of_life_step_linux.c Normal file
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// ==============================================================
// Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2025.1 (64-bit)
// Tool Version Limit: 2025.05
// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
// Copyright 2022-2025 Advanced Micro Devices, Inc. All Rights Reserved.
//
// ==============================================================
#ifdef __linux__
/***************************** Include Files *********************************/
#include "xgame_of_life_step.h"
/***************** Macros (Inline Functions) Definitions *********************/
#define MAX_UIO_PATH_SIZE 256
#define MAX_UIO_NAME_SIZE 64
#define MAX_UIO_MAPS 5
#define UIO_INVALID_ADDR 0
/**************************** Type Definitions ******************************/
typedef struct {
u64 addr;
u32 size;
} XGame_of_life_step_uio_map;
typedef struct {
int uio_fd;
int uio_num;
char name[ MAX_UIO_NAME_SIZE ];
char version[ MAX_UIO_NAME_SIZE ];
XGame_of_life_step_uio_map maps[ MAX_UIO_MAPS ];
} XGame_of_life_step_uio_info;
/***************** Variable Definitions **************************************/
static XGame_of_life_step_uio_info uio_info;
/************************** Function Implementation *************************/
static int line_from_file(char* filename, char* linebuf) {
char* s;
int i;
FILE* fp = fopen(filename, "r");
if (!fp) return -1;
s = fgets(linebuf, MAX_UIO_NAME_SIZE, fp);
fclose(fp);
if (!s) return -2;
for (i=0; (*s)&&(i<MAX_UIO_NAME_SIZE); i++) {
if (*s == '\n') *s = 0;
s++;
}
return 0;
}
static int uio_info_read_name(XGame_of_life_step_uio_info* info) {
char file[ MAX_UIO_PATH_SIZE ];
sprintf(file, "/sys/class/uio/uio%d/name", info->uio_num);
return line_from_file(file, info->name);
}
static int uio_info_read_version(XGame_of_life_step_uio_info* info) {
char file[ MAX_UIO_PATH_SIZE ];
sprintf(file, "/sys/class/uio/uio%d/version", info->uio_num);
return line_from_file(file, info->version);
}
static int uio_info_read_map_addr(XGame_of_life_step_uio_info* info, int n) {
int ret;
char file[ MAX_UIO_PATH_SIZE ];
info->maps[n].addr = UIO_INVALID_ADDR;
sprintf(file, "/sys/class/uio/uio%d/maps/map%d/addr", info->uio_num, n);
FILE* fp = fopen(file, "r");
if (!fp) return -1;
ret = fscanf(fp, "0x%x", &info->maps[n].addr);
fclose(fp);
if (ret < 0) return -2;
return 0;
}
static int uio_info_read_map_size(XGame_of_life_step_uio_info* info, int n) {
int ret;
char file[ MAX_UIO_PATH_SIZE ];
sprintf(file, "/sys/class/uio/uio%d/maps/map%d/size", info->uio_num, n);
FILE* fp = fopen(file, "r");
if (!fp) return -1;
ret = fscanf(fp, "0x%x", &info->maps[n].size);
fclose(fp);
if (ret < 0) return -2;
return 0;
}
int XGame_of_life_step_Initialize(XGame_of_life_step *InstancePtr, const char* InstanceName) {
XGame_of_life_step_uio_info *InfoPtr = &uio_info;
struct dirent **namelist;
int i, n;
char* s;
char file[ MAX_UIO_PATH_SIZE ];
char name[ MAX_UIO_NAME_SIZE ];
int flag = 0;
assert(InstancePtr != NULL);
n = scandir("/sys/class/uio", &namelist, 0, alphasort);
if (n < 0) return XST_DEVICE_NOT_FOUND;
for (i = 0; i < n; i++) {
strcpy(file, "/sys/class/uio/");
strcat(file, namelist[i]->d_name);
strcat(file, "/name");
if ((line_from_file(file, name) == 0) && (strcmp(name, InstanceName) == 0)) {
flag = 1;
s = namelist[i]->d_name;
s += 3; // "uio"
InfoPtr->uio_num = atoi(s);
break;
}
}
if (flag == 0) return XST_DEVICE_NOT_FOUND;
uio_info_read_name(InfoPtr);
uio_info_read_version(InfoPtr);
for (n = 0; n < MAX_UIO_MAPS; ++n) {
uio_info_read_map_addr(InfoPtr, n);
uio_info_read_map_size(InfoPtr, n);
}
sprintf(file, "/dev/uio%d", InfoPtr->uio_num);
if ((InfoPtr->uio_fd = open(file, O_RDWR)) < 0) {
return XST_OPEN_DEVICE_FAILED;
}
// NOTE: slave interface 'Axilites' should be mapped to uioX/map0
InstancePtr->Axilites_BaseAddress = (u64)mmap(NULL, InfoPtr->maps[0].size, PROT_READ|PROT_WRITE, MAP_SHARED, InfoPtr->uio_fd, 0 * getpagesize());
assert(InstancePtr->Axilites_BaseAddress);
InstancePtr->IsReady = XIL_COMPONENT_IS_READY;
return XST_SUCCESS;
}
int XGame_of_life_step_Release(XGame_of_life_step *InstancePtr) {
XGame_of_life_step_uio_info *InfoPtr = &uio_info;
assert(InstancePtr != NULL);
assert(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
munmap((void*)InstancePtr->Axilites_BaseAddress, InfoPtr->maps[0].size);
close(InfoPtr->uio_fd);
return XST_SUCCESS;
}
#endif

79
Practicals/practical-3b/game_of_life_practical3b/game_of_life_practical3b/hls/.autopilot/db/driver/src/xgame_of_life_step_sinit.c Normal file
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// ==============================================================
// Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2025.1 (64-bit)
// Tool Version Limit: 2025.05
// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
// Copyright 2022-2025 Advanced Micro Devices, Inc. All Rights Reserved.
//
// ==============================================================
#ifndef __linux__
#include "xstatus.h"
#ifdef SDT
#include "xparameters.h"
#endif
#include "xgame_of_life_step.h"
extern XGame_of_life_step_Config XGame_of_life_step_ConfigTable[];
#ifdef SDT
XGame_of_life_step_Config *XGame_of_life_step_LookupConfig(UINTPTR BaseAddress) {
XGame_of_life_step_Config *ConfigPtr = NULL;
int Index;
for (Index = (u32)0x0; XGame_of_life_step_ConfigTable[Index].Name != NULL; Index++) {
if (!BaseAddress || XGame_of_life_step_ConfigTable[Index].Axilites_BaseAddress == BaseAddress) {
ConfigPtr = &XGame_of_life_step_ConfigTable[Index];
break;
}
}
return ConfigPtr;
}
int XGame_of_life_step_Initialize(XGame_of_life_step *InstancePtr, UINTPTR BaseAddress) {
XGame_of_life_step_Config *ConfigPtr;
Xil_AssertNonvoid(InstancePtr != NULL);
ConfigPtr = XGame_of_life_step_LookupConfig(BaseAddress);
if (ConfigPtr == NULL) {
InstancePtr->IsReady = 0;
return (XST_DEVICE_NOT_FOUND);
}
return XGame_of_life_step_CfgInitialize(InstancePtr, ConfigPtr);
}
#else
XGame_of_life_step_Config *XGame_of_life_step_LookupConfig(u16 DeviceId) {
XGame_of_life_step_Config *ConfigPtr = NULL;
int Index;
for (Index = 0; Index < XPAR_XGAME_OF_LIFE_STEP_NUM_INSTANCES; Index++) {
if (XGame_of_life_step_ConfigTable[Index].DeviceId == DeviceId) {
ConfigPtr = &XGame_of_life_step_ConfigTable[Index];
break;
}
}
return ConfigPtr;
}
int XGame_of_life_step_Initialize(XGame_of_life_step *InstancePtr, u16 DeviceId) {
XGame_of_life_step_Config *ConfigPtr;
Xil_AssertNonvoid(InstancePtr != NULL);
ConfigPtr = XGame_of_life_step_LookupConfig(DeviceId);
if (ConfigPtr == NULL) {
InstancePtr->IsReady = 0;
return (XST_DEVICE_NOT_FOUND);
}
return XGame_of_life_step_CfgInitialize(InstancePtr, ConfigPtr);
}
#endif
#endif

1
Practicals/practical-3b/game_of_life_practical3b/game_of_life_practical3b/hls/.autopilot/db/dsp_style Normal file
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DSP48E1

BIN
Practicals/practical-3b/game_of_life_practical3b/game_of_life_practical3b/hls/.autopilot/db/dut.hcp Normal file
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90
Practicals/practical-3b/game_of_life_practical3b/game_of_life_practical3b/hls/.autopilot/db/fe_messages.xml Normal file
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<xilinx:hls_fe_msgs>
<msg msg_groups="PRAGMA_VERBOSE_DUMP" msg_id="207-5471" msg_severity="WARNING" msg_loc="directive:1:9" msg_body="HLS pragma dump">
<args ARG_PragmaContext="directive" ARG_PragmaFunction="game_of_life_step" ARG_PragmaIsValid="1" ARG_PragmaOptions="name=game_of_life_step" ARG_PragmaType="top" ClangWarningOption="dump-hls-pragmas"/>
</msg>
<msg msg_groups="PRAGMA_VERBOSE_DUMP" msg_id="207-5471" msg_severity="WARNING" msg_loc="gameoflife.cpp:6:9" msg_body="HLS pragma dump">
<args ARG_PragmaFunction="game_of_life_step" ARG_PragmaIsValid="1" ARG_PragmaOptions="variable=in_words dim=1 type=complete" ARG_PragmaType="array_partition" ClangWarningOption="dump-hls-pragmas"/>
</msg>
<msg msg_groups="PRAGMA_VERBOSE_DUMP" msg_id="207-5471" msg_severity="WARNING" msg_loc="gameoflife.cpp:7:9" msg_body="HLS pragma dump">
<args ARG_PragmaFunction="game_of_life_step" ARG_PragmaIsValid="1" ARG_PragmaOptions="variable=out_words dim=1 type=complete" ARG_PragmaType="array_partition" ClangWarningOption="dump-hls-pragmas"/>
</msg>
<msg msg_groups="PRAGMA_VERBOSE_DUMP" msg_id="207-5471" msg_severity="WARNING" msg_loc="gameoflife.cpp:9:9" msg_body="HLS pragma dump">
<args ARG_PragmaFunction="game_of_life_step" ARG_PragmaIsValid="1" ARG_PragmaOptions="s_axilite port = in_words bundle = AXILiteS" ARG_PragmaType="interface" ClangWarningOption="dump-hls-pragmas"/>
</msg>
<msg msg_groups="PRAGMA_VERBOSE_DUMP" msg_id="207-5471" msg_severity="WARNING" msg_loc="gameoflife.cpp:10:9" msg_body="HLS pragma dump">
<args ARG_PragmaFunction="game_of_life_step" ARG_PragmaIsValid="1" ARG_PragmaOptions="s_axilite port = out_words bundle = AXILiteS" ARG_PragmaType="interface" ClangWarningOption="dump-hls-pragmas"/>
</msg>
<msg msg_groups="PRAGMA_VERBOSE_DUMP" msg_id="207-5471" msg_severity="WARNING" msg_loc="gameoflife.cpp:11:9" msg_body="HLS pragma dump">
<args ARG_PragmaFunction="game_of_life_step" ARG_PragmaIsValid="1" ARG_PragmaOptions="s_axilite port = return bundle = AXILiteS" ARG_PragmaType="interface" ClangWarningOption="dump-hls-pragmas"/>
</msg>
<msg msg_groups="PRAGMA_VERBOSE_DUMP" msg_id="207-5471" msg_severity="WARNING" msg_loc="gameoflife.cpp:15:9" msg_body="HLS pragma dump">
<args ARG_PragmaFunction="game_of_life_step" ARG_PragmaIsValid="1" ARG_PragmaOptions="variable=current_grid dim=0 type=complete" ARG_PragmaType="array_partition" ClangWarningOption="dump-hls-pragmas"/>
</msg>
<msg msg_groups="PRAGMA_VERBOSE_DUMP" msg_id="207-5471" msg_severity="WARNING" msg_loc="gameoflife.cpp:19:9" msg_body="HLS pragma dump">
<args ARG_PragmaFunction="game_of_life_step" ARG_PragmaIsValid="1" ARG_PragmaOptions="variable=next_grid dim=0 type=complete" ARG_PragmaType="array_partition" ClangWarningOption="dump-hls-pragmas"/>
</msg>
<msg msg_groups="PRAGMA_VERBOSE_DUMP" msg_id="207-5471" msg_severity="WARNING" msg_loc="gameoflife.cpp:28:9" msg_body="HLS pragma dump">
<args ARG_PragmaFunction="game_of_life_step" ARG_PragmaIsValid="1" ARG_PragmaType="unroll" ClangWarningOption="dump-hls-pragmas"/>
</msg>
<msg msg_groups="PRAGMA_VERBOSE_DUMP" msg_id="207-5471" msg_severity="WARNING" msg_loc="gameoflife.cpp:40:9" msg_body="HLS pragma dump">
<args ARG_PragmaFunction="game_of_life_step" ARG_PragmaIsValid="1" ARG_PragmaType="unroll" ClangWarningOption="dump-hls-pragmas"/>
</msg>
<msg msg_groups="PRAGMA_VERBOSE_DUMP" msg_id="207-5471" msg_severity="WARNING" msg_loc="gameoflife.cpp:44:9" msg_body="HLS pragma dump">
<args ARG_PragmaFunction="game_of_life_step" ARG_PragmaIsValid="1" ARG_PragmaType="unroll" ClangWarningOption="dump-hls-pragmas"/>
</msg>
<msg msg_groups="PRAGMA_VERBOSE_DUMP" msg_id="207-5471" msg_severity="WARNING" msg_loc="gameoflife.cpp:51:9" msg_body="HLS pragma dump">
<args ARG_PragmaFunction="game_of_life_step" ARG_PragmaIsValid="1" ARG_PragmaType="unroll" ClangWarningOption="dump-hls-pragmas"/>
</msg>
<msg msg_groups="PRAGMA_VERBOSE_DUMP" msg_id="207-5471" msg_severity="WARNING" msg_loc="gameoflife.cpp:55:9" msg_body="HLS pragma dump">
<args ARG_PragmaFunction="game_of_life_step" ARG_PragmaIsValid="1" ARG_PragmaType="unroll" ClangWarningOption="dump-hls-pragmas"/>
</msg>
<msg msg_groups="PRAGMA_VERBOSE_DUMP" msg_id="207-5471" msg_severity="WARNING" msg_loc="gameoflife.cpp:81:9" msg_body="HLS pragma dump">
<args ARG_PragmaFunction="game_of_life_step" ARG_PragmaIsValid="1" ARG_PragmaOptions="variable=packed_words dim=1 type=complete" ARG_PragmaType="array_partition" ClangWarningOption="dump-hls-pragmas"/>
</msg>
<msg msg_groups="PRAGMA_VERBOSE_DUMP" msg_id="207-5471" msg_severity="WARNING" msg_loc="gameoflife.cpp:85:9" msg_body="HLS pragma dump">
<args ARG_PragmaFunction="game_of_life_step" ARG_PragmaIsValid="1" ARG_PragmaType="unroll" ClangWarningOption="dump-hls-pragmas"/>
</msg>
<msg msg_groups="PRAGMA_VERBOSE_DUMP" msg_id="207-5471" msg_severity="WARNING" msg_loc="gameoflife.cpp:91:9" msg_body="HLS pragma dump">
<args ARG_PragmaFunction="game_of_life_step" ARG_PragmaIsValid="1" ARG_PragmaType="unroll" ClangWarningOption="dump-hls-pragmas"/>
</msg>
<msg msg_groups="PRAGMA_VERBOSE_DUMP" msg_id="207-5471" msg_severity="WARNING" msg_loc="gameoflife.cpp:101:9" msg_body="HLS pragma dump">
<args ARG_PragmaFunction="game_of_life_step" ARG_PragmaIsValid="1" ARG_PragmaType="unroll" ClangWarningOption="dump-hls-pragmas"/>
</msg>
<msg msg_groups="PRAGMA_UNROLL" msg_id="214-186" msg_severity="INFO" msg_loc="gameoflife.cpp:5:0" msg_body="Unrolling loop 'VITIS_LOOP_100_2' (gameoflife.cpp:100:23) in function 'game_of_life_step' completely with a factor of 4">
<args Factor="4" LoopLoc="gameoflife.cpp:100:23" LoopName="VITIS_LOOP_100_2"/>
</msg>
<msg msg_groups="PRAGMA_UNROLL" msg_id="214-186" msg_severity="INFO" msg_loc="gameoflife.cpp:5:0" msg_body="Unrolling loop 'pack_direct' (gameoflife.cpp:90:5) in function 'game_of_life_step' completely with a factor of 100">
<args Factor="100" LoopLoc="gameoflife.cpp:90:5" LoopName="pack_direct"/>
</msg>
<msg msg_groups="PRAGMA_UNROLL" msg_id="214-186" msg_severity="INFO" msg_loc="gameoflife.cpp:5:0" msg_body="Unrolling loop 'VITIS_LOOP_84_1' (gameoflife.cpp:84:19) in function 'game_of_life_step' completely with a factor of 4">
<args Factor="4" LoopLoc="gameoflife.cpp:84:19" LoopName="VITIS_LOOP_84_1"/>
</msg>
<msg msg_groups="PRAGMA_UNROLL" msg_id="214-186" msg_severity="INFO" msg_loc="gameoflife.cpp:5:0" msg_body="Unrolling loop 'row_loop' (gameoflife.cpp:39:5) in function 'game_of_life_step' completely with a factor of 10">
<args Factor="10" LoopLoc="gameoflife.cpp:39:5" LoopName="row_loop"/>
</msg>
<msg msg_groups="PRAGMA_UNROLL" msg_id="214-186" msg_severity="INFO" msg_loc="gameoflife.cpp:5:0" msg_body="Unrolling loop 'column_loop' (gameoflife.cpp:43:9) in function 'game_of_life_step' completely with a factor of 10">
<args Factor="10" LoopLoc="gameoflife.cpp:43:9" LoopName="column_loop"/>
</msg>
<msg msg_groups="PRAGMA_UNROLL" msg_id="214-186" msg_severity="INFO" msg_loc="gameoflife.cpp:5:0" msg_body="Unrolling loop 'delta_row_loop' (gameoflife.cpp:50:13) in function 'game_of_life_step' completely with a factor of 3">
<args Factor="3" LoopLoc="gameoflife.cpp:50:13" LoopName="delta_row_loop"/>
</msg>
<msg msg_groups="PRAGMA_UNROLL" msg_id="214-186" msg_severity="INFO" msg_loc="gameoflife.cpp:5:0" msg_body="Unrolling loop 'delta_col_loop' (gameoflife.cpp:54:17) in function 'game_of_life_step' completely with a factor of 3">
<args Factor="3" LoopLoc="gameoflife.cpp:54:17" LoopName="delta_col_loop"/>
</msg>
<msg msg_groups="PRAGMA_UNROLL" msg_id="214-186" msg_severity="INFO" msg_loc="gameoflife.cpp:5:0" msg_body="Unrolling loop 'unpack_loop' (gameoflife.cpp:27:5) in function 'game_of_life_step' completely with a factor of 100">
<args Factor="100" LoopLoc="gameoflife.cpp:27:5" LoopName="unpack_loop"/>
</msg>
<msg msg_groups="PRAGMA_MISC" msg_id="214-248" msg_severity="INFO" msg_loc="gameoflife.cpp:14:13" msg_body="Applying array_partition to 'current_grid': Complete partitioning on dimension 1. Complete partitioning on dimension 2.">
<args Dim="islist 1 2" Mode="islist Complete Complete" UOName="current_grid"/>
</msg>
<msg msg_groups="PRAGMA_MISC" msg_id="214-248" msg_severity="INFO" msg_loc="gameoflife.cpp:18:13" msg_body="Applying array_partition to 'next_grid': Complete partitioning on dimension 1. Complete partitioning on dimension 2.">
<args Dim="islist 1 2" Mode="islist Complete Complete" UOName="next_grid"/>
</msg>
<msg msg_groups="PRAGMA_MISC" msg_id="214-248" msg_severity="INFO" msg_loc="gameoflife.cpp:5:0" msg_body="Applying array_partition to 'in_words': Complete partitioning on dimension 1.">
<args Dim="1" Mode="Complete" UOName="in_words"/>
</msg>
<msg msg_groups="PRAGMA_MISC" msg_id="214-248" msg_severity="INFO" msg_loc="gameoflife.cpp:5:0" msg_body="Applying array_partition to 'out_words': Complete partitioning on dimension 1.">
<args Dim="1" Mode="Complete" UOName="out_words"/>
</msg>
</xilinx:hls_fe_msgs>

44
Practicals/practical-3b/game_of_life_practical3b/game_of_life_practical3b/hls/.autopilot/db/fe_pragma_dump.reflow.0.xml Normal file
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@@ -0,0 +1,44 @@
<pragmas>
<pragma file="gameoflife.cpp" line="101" pragmaType="unroll" parentfunction="game_of_life_step" factor="-1" skip_exit_check="0"/>
<pragma file="gameoflife.cpp" line="91" pragmaType="unroll" parentfunction="game_of_life_step" factor="-1" skip_exit_check="0"/>
<pragma file="gameoflife.cpp" line="85" pragmaType="unroll" parentfunction="game_of_life_step" factor="-1" skip_exit_check="0"/>
<pragma file="gameoflife.cpp" line="40" pragmaType="unroll" parentfunction="game_of_life_step" factor="-1" skip_exit_check="0"/>
<pragma file="gameoflife.cpp" line="44" pragmaType="unroll" parentfunction="game_of_life_step" factor="-1" skip_exit_check="0"/>
<pragma file="gameoflife.cpp" line="51" pragmaType="unroll" parentfunction="game_of_life_step" factor="-1" skip_exit_check="0"/>
<pragma file="gameoflife.cpp" line="55" pragmaType="unroll" parentfunction="game_of_life_step" factor="-1" skip_exit_check="0"/>
<pragma file="gameoflife.cpp" line="28" pragmaType="unroll" parentfunction="game_of_life_step" factor="-1" skip_exit_check="0"/>
<pragma file="gameoflife.cpp" line="6" pragmaType="array_partition" parentfunction="game_of_life_step" dim="1" factor="0" mode="complete" dynamic="0" variable="in_words"/>
<pragma file="gameoflife.cpp" line="7" pragmaType="array_partition" parentfunction="game_of_life_step" dim="1" factor="0" mode="complete" dynamic="0" variable="out_words"/>
<pragma file="gameoflife.cpp" line="9" pragmaType="interface" parentfunction="game_of_life_step" mode="s_axilite" port="in_words" bundle="AXILiteS" offset="-1" name="" clock="" impl="" register="0"/>
<pragma file="gameoflife.cpp" line="10" pragmaType="interface" parentfunction="game_of_life_step" mode="s_axilite" port="out_words" bundle="AXILiteS" offset="-1" name="" clock="" impl="" register="0"/>
<pragma file="gameoflife.cpp" line="11" pragmaType="interface" parentfunction="game_of_life_step" mode="s_axilite" port="" bundle="AXILiteS" offset="-1" name="" clock="" impl="" register="0"/>
<pragma file="gameoflife.cpp" line="15" pragmaType="array_partition" parentfunction="game_of_life_step" dim="0" factor="0" mode="complete" dynamic="0" variable="current_grid"/>
<pragma file="gameoflife.cpp" line="19" pragmaType="array_partition" parentfunction="game_of_life_step" dim="0" factor="0" mode="complete" dynamic="0" variable="next_grid"/>
<pragma file="gameoflife.cpp" line="81" pragmaType="array_partition" parentfunction="game_of_life_step" dim="1" factor="0" mode="complete" dynamic="0" variable="packed_words"/>
<pragma file="" line="0" pragmaType="inline" parentfunction="ap_uint<4>::ap_uint(int)" off="0" region="0" recursive="0"/>
<pragma file="" line="0" pragmaType="inline" parentfunction="ap_bit_ref<32, false>& ap_bit_ref<32, false>::operator=<1, false>(ap_int_base<1, false> const&)" off="0" region="0" recursive="0"/>
<pragma file="" line="0" pragmaType="inline" parentfunction="ap_int_base<32, false>::operator unsigned long long() const" off="0" region="0" recursive="0"/>
<pragma file="" line="0" pragmaType="inline" parentfunction="checkOverflowBaseC" off="0" region="0" recursive="0"/>
<pragma file="" line="0" pragmaType="inline" parentfunction="ap_bit_ref<32, false>::ap_bit_ref(ap_int_base<32, false>*, int)" off="0" region="0" recursive="0"/>
<pragma file="" line="0" pragmaType="inline" parentfunction="ap_int_base<32, false>::ap_int_base(int)" off="0" region="0" recursive="0"/>
<pragma file="" line="0" pragmaType="inline" parentfunction="checkOverflowBaseC" off="0" region="0" recursive="0"/>
<pragma file="/opt/york/cs/net/xilinx_vivado-2025.1-x86_64-1/2025.1/Vitis/common/technology/autopilot/etc/ap_common.h" line="542" pragmaType="inline" parentfunction="ssdm_int<32, false>::ssdm_int(unsigned int)" off="0" region="0" recursive="0"/>
<pragma file="" line="0" pragmaType="inline" parentfunction="ap_int_base<32, true>::ap_int_base(int)" off="0" region="0" recursive="0"/>
<pragma file="" line="0" pragmaType="inline" parentfunction="bool ap_int_base<4, false>::operator==<32, true>(ap_int_base<32, true> const&) const" off="0" region="0" recursive="0"/>
<pragma file="/opt/york/cs/net/xilinx_vivado-2025.1-x86_64-1/2025.1/Vitis/common/technology/autopilot/etc/ap_common.h" line="534" pragmaType="inline" parentfunction="ssdm_int<32, true>::ssdm_int(int)" off="0" region="0" recursive="0"/>
<pragma file="" line="0" pragmaType="inline" parentfunction="ap_int_base<4, false>::ap_int_base(int)" off="0" region="0" recursive="0"/>
<pragma file="" line="0" pragmaType="inline" parentfunction="checkOverflowBaseC" off="0" region="0" recursive="0"/>
<pragma file="/opt/york/cs/net/xilinx_vivado-2025.1-x86_64-1/2025.1/Vitis/common/technology/autopilot/etc/ap_common.h" line="542" pragmaType="inline" parentfunction="_ZN8ssdm_intILi4ELb0EEC2EDq4_j" off="0" region="0" recursive="0"/>
<pragma file="" line="0" pragmaType="inline" parentfunction="ap_int_base<1, false>::ap_int_base(unsigned int)" off="0" region="0" recursive="0"/>
<pragma file="" line="0" pragmaType="inline" parentfunction="ap_int_base<1, false>::operator unsigned long long() const" off="0" region="0" recursive="0"/>
<pragma file="" line="0" pragmaType="inline" parentfunction="bool operator==<4, false>(ap_int_base<4, false> const&, int)" off="0" region="0" recursive="0"/>
<pragma file="" line="0" pragmaType="inline" parentfunction="ap_uint<1>::ap_uint(bool)" off="0" region="0" recursive="0"/>
<pragma file="" line="0" pragmaType="inline" parentfunction="ap_uint<32>::ap_uint(int)" off="0" region="0" recursive="0"/>
<pragma file="" line="0" pragmaType="inline" parentfunction="ap_int_base<32, false>::operator[](int)" off="0" region="0" recursive="0"/>
<pragma file="" line="0" pragmaType="inline" parentfunction="checkOverflowBaseC" off="0" region="0" recursive="0"/>
<pragma file="" line="0" pragmaType="inline" parentfunction="ap_bit_ref<32, false>::operator=(unsigned long long)" off="0" region="0" recursive="0"/>
<pragma file="" line="0" pragmaType="inline" parentfunction="ap_int_base<1, false>::ap_int_base(bool)" off="0" region="0" recursive="0"/>
<pragma file="/opt/york/cs/net/xilinx_vivado-2025.1-x86_64-1/2025.1/Vitis/common/technology/autopilot/etc/ap_common.h" line="542" pragmaType="inline" parentfunction="_ZN8ssdm_intILi1ELb0EEC2EDq1_j" off="0" region="0" recursive="0"/>
<pragma file="" line="0" pragmaType="inline" parentfunction="ap_int_base<4, false>& ap_int_base<4, false>::operator+=<1, false>(ap_int_base<1, false> const&)" off="0" region="0" recursive="0"/>
<pragma file="" line="0" pragmaType="inline" parentfunction="ap_uint<1>::ap_uint(unsigned int)" off="0" region="0" recursive="0"/>
</pragmas>

6
Practicals/practical-3b/game_of_life_practical3b/game_of_life_practical3b/hls/.autopilot/db/game_of_life_step.DependenceCheck.tcl Normal file
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set RtlHierarchyInfo {[
{"ID" : "0", "Level" : "0", "Path" : "`AUTOTB_DUT_INST"},
{"ID" : "1", "Level" : "1", "Path" : "`AUTOTB_DUT_INST.AXILiteS_s_axi_U"}]}
set DependenceCheckSize 0

211851
Practicals/practical-3b/game_of_life_practical3b/game_of_life_practical3b/hls/.autopilot/db/game_of_life_step.adb Normal file
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32459
Practicals/practical-3b/game_of_life_practical3b/game_of_life_practical3b/hls/.autopilot/db/game_of_life_step.adb.xml Normal file
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176970
Practicals/practical-3b/game_of_life_practical3b/game_of_life_practical3b/hls/.autopilot/db/game_of_life_step.bind.adb Normal file
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32459
Practicals/practical-3b/game_of_life_practical3b/game_of_life_practical3b/hls/.autopilot/db/game_of_life_step.bind.adb.xml Normal file
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78
Practicals/practical-3b/game_of_life_practical3b/game_of_life_practical3b/hls/.autopilot/db/game_of_life_step.compgen.dataonly.tcl Normal file
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@@ -0,0 +1,78 @@
# This script segment is generated automatically by AutoPilot
set axilite_register_dict [dict create]
set port_AXILiteS {
in_words_0 {
dir I
width 32
depth 1
mode ap_none
offset 16
offset_end 23
}
in_words_1 {
dir I
width 32
depth 1
mode ap_none
offset 24
offset_end 31
}
in_words_2 {
dir I
width 32
depth 1
mode ap_none
offset 32
offset_end 39
}
in_words_3 {
dir I
width 32
depth 1
mode ap_none
offset 40
offset_end 47
}
out_words_0 {
dir O
width 32
depth 1
mode ap_vld
offset 48
offset_end 55
}
out_words_1 {
dir O
width 32
depth 1
mode ap_vld
offset 64
offset_end 71
}
out_words_2 {
dir O
width 32
depth 1
mode ap_vld
offset 80
offset_end 87
}
out_words_3 {
dir O
width 32
depth 1
mode ap_vld
offset 96
offset_end 103
}
ap_start { }
ap_done { }
ap_ready { }
ap_idle { }
interrupt {
}
}
dict set axilite_register_dict AXILiteS $port_AXILiteS

160
Practicals/practical-3b/game_of_life_practical3b/game_of_life_practical3b/hls/.autopilot/db/game_of_life_step.compgen.tcl Normal file
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# This script segment is generated automatically by AutoPilot
# clear list
if {${::AESL::PGuard_autoexp_gen}} {
cg_default_interface_gen_dc_begin
cg_default_interface_gen_bundle_begin
AESL_LIB_XILADAPTER::native_axis_begin
}
set axilite_register_dict [dict create]
set port_AXILiteS {
in_words_0 {
dir I
width 32
depth 1
mode ap_none
offset 16
offset_end 23
}
in_words_1 {
dir I
width 32
depth 1
mode ap_none
offset 24
offset_end 31
}
in_words_2 {
dir I
width 32
depth 1
mode ap_none
offset 32
offset_end 39
}
in_words_3 {
dir I
width 32
depth 1
mode ap_none
offset 40
offset_end 47
}
out_words_0 {
dir O
width 32
depth 1
mode ap_vld
offset 48
offset_end 55
}
out_words_1 {
dir O
width 32
depth 1
mode ap_vld
offset 64
offset_end 71
}
out_words_2 {
dir O
width 32
depth 1
mode ap_vld
offset 80
offset_end 87
}
out_words_3 {
dir O
width 32
depth 1
mode ap_vld
offset 96
offset_end 103
}
ap_start { }
ap_done { }
ap_ready { }
ap_idle { }
interrupt {
}
}
dict set axilite_register_dict AXILiteS $port_AXILiteS
# Native S_AXILite:
if {${::AESL::PGuard_simmodel_gen}} {
if {[info proc ::AESL_LIB_XILADAPTER::s_axilite_gen] == "::AESL_LIB_XILADAPTER::s_axilite_gen"} {
eval "::AESL_LIB_XILADAPTER::s_axilite_gen { \
id 1 \
corename game_of_life_step_AXILiteS_axilite \
name game_of_life_step_AXILiteS_s_axi \
ports {$port_AXILiteS} \
op interface \
interrupt_clear_mode TOW \
interrupt_trigger_type default \
is_flushable 0 \
is_datawidth64 0 \
is_addrwidth64 1 \
enable_mem_auto_widen 1 \
} "
} else {
puts "@W \[IMPL-110\] Cannot find AXI Lite interface model in the library. Ignored generation of AXI Lite interface for 'AXILiteS'"
}
}
if {${::AESL::PGuard_rtl_comp_handler}} {
::AP::rtl_comp_handler game_of_life_step_AXILiteS_s_axi BINDTYPE interface TYPE interface_s_axilite
}
# Adapter definition:
set PortName ap_clk
set DataWd 1
if {${::AESL::PGuard_autoexp_gen}} {
if {[info proc cg_default_interface_gen_clock] == "cg_default_interface_gen_clock"} {
eval "cg_default_interface_gen_clock { \
id -1 \
name ${PortName} \
reset_level 0 \
sync_rst true \
corename apif_ap_clk \
data_wd ${DataWd} \
op interface \
}"
} else {
puts "@W \[IMPL-113\] Cannot find bus interface model in the library. Ignored generation of bus interface for '${PortName}'"
}
}
# Adapter definition:
set PortName ap_rst_n
set DataWd 1
if {${::AESL::PGuard_autoexp_gen}} {
if {[info proc cg_default_interface_gen_reset] == "cg_default_interface_gen_reset"} {
eval "cg_default_interface_gen_reset { \
id -2 \
name ${PortName} \
reset_level 0 \
sync_rst true \
corename apif_ap_rst_n \
data_wd ${DataWd} \
op interface \
}"
} else {
puts "@W \[IMPL-114\] Cannot find bus interface model in the library. Ignored generation of bus interface for '${PortName}'"
}
}
# merge
if {${::AESL::PGuard_autoexp_gen}} {
cg_default_interface_gen_dc_end
cg_default_interface_gen_bundle_end
AESL_LIB_XILADAPTER::native_axis_end
}

12
Practicals/practical-3b/game_of_life_practical3b/game_of_life_practical3b/hls/.autopilot/db/game_of_life_step.constraint.tcl Normal file
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@@ -0,0 +1,12 @@
set clock_constraint { \
name clk \
module game_of_life_step \
port ap_clk \
period 10 \
uncertainty 2.7 \
}
set all_path {}
set false_path {}

282
Practicals/practical-3b/game_of_life_practical3b/game_of_life_practical3b/hls/.autopilot/db/game_of_life_step.design.xml Normal file
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@@ -0,0 +1,282 @@
<profile>
<RTLDesignHierarchy>
<TopModule>
<ModuleName>game_of_life_step</ModuleName>
</TopModule>
</RTLDesignHierarchy>
<ModuleInformation>
<Module>
<Name>game_of_life_step</Name>
<PerformanceEstimates>
<SummaryOfTimingAnalysis>
<TargetClockPeriod>10.00</TargetClockPeriod>
<ClockUncertainty>2.70</ClockUncertainty>
<EstimatedClockPeriod>6.928</EstimatedClockPeriod>
</SummaryOfTimingAnalysis>
<SummaryOfOverallLatency>
<Best-caseLatency>1</Best-caseLatency>
<Average-caseLatency>1</Average-caseLatency>
<Worst-caseLatency>1</Worst-caseLatency>
<Best-caseRealTimeLatency>10.000 ns</Best-caseRealTimeLatency>
<Average-caseRealTimeLatency>10.000 ns</Average-caseRealTimeLatency>
<Worst-caseRealTimeLatency>10.000 ns</Worst-caseRealTimeLatency>
<PipelineInitiationInterval>2</PipelineInitiationInterval>
<PipelineType>no</PipelineType>
<PerformancePragma>-</PerformancePragma>
</SummaryOfOverallLatency>
<SummaryOfViolations>
<IssueType>-</IssueType>
<ViolationType>-</ViolationType>
<SourceLocation>gameoflife.cpp:5</SourceLocation>
</SummaryOfViolations>
</PerformanceEstimates>
<AreaEstimates>
<Resources>
<BRAM_18K>0</BRAM_18K>
<AVAIL_BRAM>120</AVAIL_BRAM>
<UTIL_BRAM>0</UTIL_BRAM>
<FF>844</FF>
<AVAIL_FF>35200</AVAIL_FF>
<UTIL_FF>2</UTIL_FF>
<LUT>9696</LUT>
<AVAIL_LUT>17600</AVAIL_LUT>
<UTIL_LUT>55</UTIL_LUT>
<DSP>0</DSP>
<AVAIL_DSP>80</AVAIL_DSP>
<UTIL_DSP>0</UTIL_DSP>
<URAM>0</URAM>
<AVAIL_URAM>0</AVAIL_URAM>
<UTIL_URAM>0</UTIL_URAM>
</Resources>
</AreaEstimates>
<InterfaceSummary>
<RtlPorts>
<name>s_axi_AXILiteS_AWVALID</name>
<Object>AXILiteS</Object>
<Type>pointer</Type>
<IOProtocol>s_axi</IOProtocol>
<Dir>in</Dir>
<Bits>1</Bits>
<Attribute>unknown</Attribute>
<CType>int</CType>
<HasCtrl>1</HasCtrl>
</RtlPorts>
<RtlPorts>
<name>s_axi_AXILiteS_AWREADY</name>
<Object>AXILiteS</Object>
<Type>pointer</Type>
<IOProtocol>s_axi</IOProtocol>
<Dir>out</Dir>
<Bits>1</Bits>
<Attribute>unknown</Attribute>
<CType>int</CType>
<HasCtrl>1</HasCtrl>
</RtlPorts>
<RtlPorts>
<name>s_axi_AXILiteS_AWADDR</name>
<Object>AXILiteS</Object>
<Type>pointer</Type>
<IOProtocol>s_axi</IOProtocol>
<Dir>in</Dir>
<Bits>7</Bits>
<Attribute>unknown</Attribute>
<CType>int</CType>
<HasCtrl>1</HasCtrl>
</RtlPorts>
<RtlPorts>
<name>s_axi_AXILiteS_WVALID</name>
<Object>AXILiteS</Object>
<Type>pointer</Type>
<IOProtocol>s_axi</IOProtocol>
<Dir>in</Dir>
<Bits>1</Bits>
<Attribute>unknown</Attribute>
<CType>int</CType>
<HasCtrl>1</HasCtrl>
</RtlPorts>
<RtlPorts>
<name>s_axi_AXILiteS_WREADY</name>
<Object>AXILiteS</Object>
<Type>pointer</Type>
<IOProtocol>s_axi</IOProtocol>
<Dir>out</Dir>
<Bits>1</Bits>
<Attribute>unknown</Attribute>
<CType>int</CType>
<HasCtrl>1</HasCtrl>
</RtlPorts>
<RtlPorts>
<name>s_axi_AXILiteS_WDATA</name>
<Object>AXILiteS</Object>
<Type>pointer</Type>
<IOProtocol>s_axi</IOProtocol>
<Dir>in</Dir>
<Bits>32</Bits>
<Attribute>unknown</Attribute>
<CType>int</CType>
<HasCtrl>1</HasCtrl>
</RtlPorts>
<RtlPorts>
<name>s_axi_AXILiteS_WSTRB</name>
<Object>AXILiteS</Object>
<Type>pointer</Type>
<IOProtocol>s_axi</IOProtocol>
<Dir>in</Dir>
<Bits>4</Bits>
<Attribute>unknown</Attribute>
<CType>int</CType>
<HasCtrl>1</HasCtrl>
</RtlPorts>
<RtlPorts>
<name>s_axi_AXILiteS_ARVALID</name>
<Object>AXILiteS</Object>
<Type>pointer</Type>
<IOProtocol>s_axi</IOProtocol>
<Dir>in</Dir>
<Bits>1</Bits>
<Attribute>unknown</Attribute>
<CType>int</CType>
<HasCtrl>1</HasCtrl>
</RtlPorts>
<RtlPorts>
<name>s_axi_AXILiteS_ARREADY</name>
<Object>AXILiteS</Object>
<Type>pointer</Type>
<IOProtocol>s_axi</IOProtocol>
<Dir>out</Dir>
<Bits>1</Bits>
<Attribute>unknown</Attribute>
<CType>int</CType>
<HasCtrl>1</HasCtrl>
</RtlPorts>
<RtlPorts>
<name>s_axi_AXILiteS_ARADDR</name>
<Object>AXILiteS</Object>
<Type>pointer</Type>
<IOProtocol>s_axi</IOProtocol>
<Dir>in</Dir>
<Bits>7</Bits>
<Attribute>unknown</Attribute>
<CType>int</CType>
<HasCtrl>1</HasCtrl>
</RtlPorts>
<RtlPorts>
<name>s_axi_AXILiteS_RVALID</name>
<Object>AXILiteS</Object>
<Type>pointer</Type>
<IOProtocol>s_axi</IOProtocol>
<Dir>out</Dir>
<Bits>1</Bits>
<Attribute>unknown</Attribute>
<CType>int</CType>
<HasCtrl>1</HasCtrl>
</RtlPorts>
<RtlPorts>
<name>s_axi_AXILiteS_RREADY</name>
<Object>AXILiteS</Object>
<Type>pointer</Type>
<IOProtocol>s_axi</IOProtocol>
<Dir>in</Dir>
<Bits>1</Bits>
<Attribute>unknown</Attribute>
<CType>int</CType>
<HasCtrl>1</HasCtrl>
</RtlPorts>
<RtlPorts>
<name>s_axi_AXILiteS_RDATA</name>
<Object>AXILiteS</Object>
<Type>pointer</Type>
<IOProtocol>s_axi</IOProtocol>
<Dir>out</Dir>
<Bits>32</Bits>
<Attribute>unknown</Attribute>
<CType>int</CType>
<HasCtrl>1</HasCtrl>
</RtlPorts>
<RtlPorts>
<name>s_axi_AXILiteS_RRESP</name>
<Object>AXILiteS</Object>
<Type>pointer</Type>
<IOProtocol>s_axi</IOProtocol>
<Dir>out</Dir>
<Bits>2</Bits>
<Attribute>unknown</Attribute>
<CType>int</CType>
<HasCtrl>1</HasCtrl>
</RtlPorts>
<RtlPorts>
<name>s_axi_AXILiteS_BVALID</name>
<Object>AXILiteS</Object>
<Type>pointer</Type>
<IOProtocol>s_axi</IOProtocol>
<Dir>out</Dir>
<Bits>1</Bits>
<Attribute>unknown</Attribute>
<CType>int</CType>
<HasCtrl>1</HasCtrl>
</RtlPorts>
<RtlPorts>
<name>s_axi_AXILiteS_BREADY</name>
<Object>AXILiteS</Object>
<Type>pointer</Type>
<IOProtocol>s_axi</IOProtocol>
<Dir>in</Dir>
<Bits>1</Bits>
<Attribute>unknown</Attribute>
<CType>int</CType>
<HasCtrl>1</HasCtrl>
</RtlPorts>
<RtlPorts>
<name>s_axi_AXILiteS_BRESP</name>
<Object>AXILiteS</Object>
<Type>pointer</Type>
<IOProtocol>s_axi</IOProtocol>
<Dir>out</Dir>
<Bits>2</Bits>
<Attribute>unknown</Attribute>
<CType>int</CType>
<HasCtrl>1</HasCtrl>
</RtlPorts>
<RtlPorts>
<name>ap_clk</name>
<Object>game_of_life_step</Object>
<Type>return value</Type>
<Scope></Scope>
<IOProtocol>ap_ctrl_hs</IOProtocol>
<IOConfig></IOConfig>
<Dir>in</Dir>
<Bits>1</Bits>
<Attribute>control</Attribute>
</RtlPorts>
<RtlPorts>
<name>ap_rst_n</name>
<Object>game_of_life_step</Object>
<Type>return value</Type>
<Scope></Scope>
<IOProtocol>ap_ctrl_hs</IOProtocol>
<IOConfig></IOConfig>
<Dir>in</Dir>
<Bits>1</Bits>
<Attribute>control</Attribute>
</RtlPorts>
<RtlPorts>
<name>interrupt</name>
<Object>game_of_life_step</Object>
<Type>return value</Type>
<Scope></Scope>
<IOProtocol>ap_ctrl_hs</IOProtocol>
<IOConfig></IOConfig>
<Dir>out</Dir>
<Bits>1</Bits>
<Attribute>unknown</Attribute>
</RtlPorts>
</InterfaceSummary>
</Module>
</ModuleInformation>
<FIFOInformation>
</FIFOInformation>
</profile>

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{
"version": "1.0",
"modules": {
"game_of_life_step": {
"proto_instances": {
"/AESL_inst_game_of_life_step_activity": {
"interface": "xilinx.com:interface:internal_hls_dataflow:1.0",
"ports": {
"AP_CLK": { "actual": "ap_clk"},
"AP_DONE": { "actual": "ap_done"},
"AP_READY": { "actual": "ap_ready"},
"AP_RESET": { "actual": "ap_rst_n"},
"AP_START": { "actual": "ap_start"}
}
}
}
}
}
}

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set lang "C"
set moduleName "game_of_life_step"
set moduleIsExternC "1"
set rawDecl ""
set globalVariable ""
set PortList ""
set PortName "in_words_0"
set BitWidth "32"
set ArrayOpt ""
set Const "0"
set Volatile "1"
set Pointer "1"
set Reference "0"
set Dims [list 0]
set Interface "wire"
set DataType "void"
set Port [list $PortName $Interface $DataType $Pointer $Dims $Const $Volatile $ArrayOpt]
lappend PortList $Port
set PortName "in_words_1"
set BitWidth "32"
set ArrayOpt ""
set Const "0"
set Volatile "1"
set Pointer "1"
set Reference "0"
set Dims [list 0]
set Interface "wire"
set DataType "void"
set Port [list $PortName $Interface $DataType $Pointer $Dims $Const $Volatile $ArrayOpt]
lappend PortList $Port
set PortName "in_words_2"
set BitWidth "32"
set ArrayOpt ""
set Const "0"
set Volatile "1"
set Pointer "1"
set Reference "0"
set Dims [list 0]
set Interface "wire"
set DataType "void"
set Port [list $PortName $Interface $DataType $Pointer $Dims $Const $Volatile $ArrayOpt]
lappend PortList $Port
set PortName "in_words_3"
set BitWidth "32"
set ArrayOpt ""
set Const "0"
set Volatile "1"
set Pointer "1"
set Reference "0"
set Dims [list 0]
set Interface "wire"
set DataType "void"
set Port [list $PortName $Interface $DataType $Pointer $Dims $Const $Volatile $ArrayOpt]
lappend PortList $Port
set PortName "out_words_0"
set BitWidth "32"
set ArrayOpt ""
set Const "0"
set Volatile "1"
set Pointer "1"
set Reference "0"
set Dims [list 0]
set Interface "wire"
set DataType "void"
set Port [list $PortName $Interface $DataType $Pointer $Dims $Const $Volatile $ArrayOpt]
lappend PortList $Port
set PortName "out_words_1"
set BitWidth "32"
set ArrayOpt ""
set Const "0"
set Volatile "1"
set Pointer "1"
set Reference "0"
set Dims [list 0]
set Interface "wire"
set DataType "void"
set Port [list $PortName $Interface $DataType $Pointer $Dims $Const $Volatile $ArrayOpt]
lappend PortList $Port
set PortName "out_words_2"
set BitWidth "32"
set ArrayOpt ""
set Const "0"
set Volatile "1"
set Pointer "1"
set Reference "0"
set Dims [list 0]
set Interface "wire"
set DataType "void"
set Port [list $PortName $Interface $DataType $Pointer $Dims $Const $Volatile $ArrayOpt]
lappend PortList $Port
set PortName "out_words_3"
set BitWidth "32"
set ArrayOpt ""
set Const "0"
set Volatile "1"
set Pointer "1"
set Reference "0"
set Dims [list 0]
set Interface "wire"
set DataType "void"
set Port [list $PortName $Interface $DataType $Pointer $Dims $Const $Volatile $ArrayOpt]
lappend PortList $Port
set globalAPint ""
set returnAPInt ""
set hasCPPAPInt 0
set argAPInt ""
set hasCPPAPFix 0
set hasSCFix 0
set hasCBool 0
set hasCPPComplex 0
set isTemplateTop 0
set hasHalf 0
set dataPackList ""
set module [list $moduleName $PortList $rawDecl $argAPInt $returnAPInt $dataPackList]

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set moduleName game_of_life_step
set isTopModule 1
set isCombinational 0
set isDatapathOnly 0
set isPipelined 0
set isPipelined_legacy 0
set pipeline_type none
set FunctionProtocol ap_ctrl_hs
set isOneStateSeq 0
set ProfileFlag 0
set StallSigGenFlag 0
set isEnableWaveformDebug 1
set hasInterrupt 0
set DLRegFirstOffset 0
set DLRegItemOffset 0
set svuvm_can_support 1
set cdfgNum 2
set C_modelName {game_of_life_step}
set C_modelType { void 0 }
set ap_memory_interface_dict [dict create]
set C_modelArgList {
{ in_words_0 int 32 regular {axi_slave 0} }
{ in_words_1 int 32 regular {axi_slave 0} }
{ in_words_2 int 32 regular {axi_slave 0} }
{ in_words_3 int 32 regular {axi_slave 0} }
{ out_words_0 int 32 regular {axi_slave 1} }
{ out_words_1 int 32 regular {axi_slave 1} }
{ out_words_2 int 32 regular {axi_slave 1} }
{ out_words_3 int 32 regular {axi_slave 1} }
}
set hasAXIMCache 0
set l_AXIML2Cache [list]
set AXIMCacheInstDict [dict create]
set C_modelArgMapList {[
{ "Name" : "in_words_0", "interface" : "axi_slave", "bundle":"AXILiteS","type":"ap_none","bitwidth" : 32, "direction" : "READONLY", "offset" : {"in":16}, "offset_end" : {"in":23}} ,
{ "Name" : "in_words_1", "interface" : "axi_slave", "bundle":"AXILiteS","type":"ap_none","bitwidth" : 32, "direction" : "READONLY", "offset" : {"in":24}, "offset_end" : {"in":31}} ,
{ "Name" : "in_words_2", "interface" : "axi_slave", "bundle":"AXILiteS","type":"ap_none","bitwidth" : 32, "direction" : "READONLY", "offset" : {"in":32}, "offset_end" : {"in":39}} ,
{ "Name" : "in_words_3", "interface" : "axi_slave", "bundle":"AXILiteS","type":"ap_none","bitwidth" : 32, "direction" : "READONLY", "offset" : {"in":40}, "offset_end" : {"in":47}} ,
{ "Name" : "out_words_0", "interface" : "axi_slave", "bundle":"AXILiteS","type":"ap_vld","bitwidth" : 32, "direction" : "WRITEONLY", "offset" : {"out":48}, "offset_end" : {"out":55}} ,
{ "Name" : "out_words_1", "interface" : "axi_slave", "bundle":"AXILiteS","type":"ap_vld","bitwidth" : 32, "direction" : "WRITEONLY", "offset" : {"out":64}, "offset_end" : {"out":71}} ,
{ "Name" : "out_words_2", "interface" : "axi_slave", "bundle":"AXILiteS","type":"ap_vld","bitwidth" : 32, "direction" : "WRITEONLY", "offset" : {"out":80}, "offset_end" : {"out":87}} ,
{ "Name" : "out_words_3", "interface" : "axi_slave", "bundle":"AXILiteS","type":"ap_vld","bitwidth" : 32, "direction" : "WRITEONLY", "offset" : {"out":96}, "offset_end" : {"out":103}} ]}
# RTL Port declarations:
set portNum 20
set portList {
{ ap_clk sc_in sc_logic 1 clock -1 }
{ ap_rst_n sc_in sc_logic 1 reset -1 active_low_sync }
{ s_axi_AXILiteS_AWVALID sc_in sc_logic 1 signal -1 }
{ s_axi_AXILiteS_AWREADY sc_out sc_logic 1 signal -1 }
{ s_axi_AXILiteS_AWADDR sc_in sc_lv 7 signal -1 }
{ s_axi_AXILiteS_WVALID sc_in sc_logic 1 signal -1 }
{ s_axi_AXILiteS_WREADY sc_out sc_logic 1 signal -1 }
{ s_axi_AXILiteS_WDATA sc_in sc_lv 32 signal -1 }
{ s_axi_AXILiteS_WSTRB sc_in sc_lv 4 signal -1 }
{ s_axi_AXILiteS_ARVALID sc_in sc_logic 1 signal -1 }
{ s_axi_AXILiteS_ARREADY sc_out sc_logic 1 signal -1 }
{ s_axi_AXILiteS_ARADDR sc_in sc_lv 7 signal -1 }
{ s_axi_AXILiteS_RVALID sc_out sc_logic 1 signal -1 }
{ s_axi_AXILiteS_RREADY sc_in sc_logic 1 signal -1 }
{ s_axi_AXILiteS_RDATA sc_out sc_lv 32 signal -1 }
{ s_axi_AXILiteS_RRESP sc_out sc_lv 2 signal -1 }
{ s_axi_AXILiteS_BVALID sc_out sc_logic 1 signal -1 }
{ s_axi_AXILiteS_BREADY sc_in sc_logic 1 signal -1 }
{ s_axi_AXILiteS_BRESP sc_out sc_lv 2 signal -1 }
{ interrupt sc_out sc_logic 1 signal -1 }
}
set NewPortList {[
{ "name": "s_axi_AXILiteS_AWADDR", "direction": "in", "datatype": "sc_lv", "bitwidth":7, "type": "signal", "bundle":{"name": "AXILiteS", "role": "AWADDR" },"address":[{"name":"game_of_life_step","role":"start","value":"0","valid_bit":"0"},{"name":"game_of_life_step","role":"continue","value":"0","valid_bit":"4"},{"name":"game_of_life_step","role":"auto_start","value":"0","valid_bit":"7"},{"name":"in_words_0","role":"data","value":"16"},{"name":"in_words_1","role":"data","value":"24"},{"name":"in_words_2","role":"data","value":"32"},{"name":"in_words_3","role":"data","value":"40"}] },
{ "name": "s_axi_AXILiteS_AWVALID", "direction": "in", "datatype": "sc_logic", "bitwidth":1, "type": "signal", "bundle":{"name": "AXILiteS", "role": "AWVALID" } },
{ "name": "s_axi_AXILiteS_AWREADY", "direction": "out", "datatype": "sc_logic", "bitwidth":1, "type": "signal", "bundle":{"name": "AXILiteS", "role": "AWREADY" } },
{ "name": "s_axi_AXILiteS_WVALID", "direction": "in", "datatype": "sc_logic", "bitwidth":1, "type": "signal", "bundle":{"name": "AXILiteS", "role": "WVALID" } },
{ "name": "s_axi_AXILiteS_WREADY", "direction": "out", "datatype": "sc_logic", "bitwidth":1, "type": "signal", "bundle":{"name": "AXILiteS", "role": "WREADY" } },
{ "name": "s_axi_AXILiteS_WDATA", "direction": "in", "datatype": "sc_lv", "bitwidth":32, "type": "signal", "bundle":{"name": "AXILiteS", "role": "WDATA" } },
{ "name": "s_axi_AXILiteS_WSTRB", "direction": "in", "datatype": "sc_lv", "bitwidth":4, "type": "signal", "bundle":{"name": "AXILiteS", "role": "WSTRB" } },
{ "name": "s_axi_AXILiteS_ARADDR", "direction": "in", "datatype": "sc_lv", "bitwidth":7, "type": "signal", "bundle":{"name": "AXILiteS", "role": "ARADDR" },"address":[{"name":"game_of_life_step","role":"start","value":"0","valid_bit":"0"},{"name":"game_of_life_step","role":"done","value":"0","valid_bit":"1"},{"name":"game_of_life_step","role":"idle","value":"0","valid_bit":"2"},{"name":"game_of_life_step","role":"ready","value":"0","valid_bit":"3"},{"name":"game_of_life_step","role":"auto_start","value":"0","valid_bit":"7"},{"name":"out_words_0","role":"data","value":"48"}, {"name":"out_words_0","role":"valid","value":"52","valid_bit":"0"},{"name":"out_words_1","role":"data","value":"64"}, {"name":"out_words_1","role":"valid","value":"68","valid_bit":"0"},{"name":"out_words_2","role":"data","value":"80"}, {"name":"out_words_2","role":"valid","value":"84","valid_bit":"0"},{"name":"out_words_3","role":"data","value":"96"}, {"name":"out_words_3","role":"valid","value":"100","valid_bit":"0"}] },
{ "name": "s_axi_AXILiteS_ARVALID", "direction": "in", "datatype": "sc_logic", "bitwidth":1, "type": "signal", "bundle":{"name": "AXILiteS", "role": "ARVALID" } },
{ "name": "s_axi_AXILiteS_ARREADY", "direction": "out", "datatype": "sc_logic", "bitwidth":1, "type": "signal", "bundle":{"name": "AXILiteS", "role": "ARREADY" } },
{ "name": "s_axi_AXILiteS_RVALID", "direction": "out", "datatype": "sc_logic", "bitwidth":1, "type": "signal", "bundle":{"name": "AXILiteS", "role": "RVALID" } },
{ "name": "s_axi_AXILiteS_RREADY", "direction": "in", "datatype": "sc_logic", "bitwidth":1, "type": "signal", "bundle":{"name": "AXILiteS", "role": "RREADY" } },
{ "name": "s_axi_AXILiteS_RDATA", "direction": "out", "datatype": "sc_lv", "bitwidth":32, "type": "signal", "bundle":{"name": "AXILiteS", "role": "RDATA" } },
{ "name": "s_axi_AXILiteS_RRESP", "direction": "out", "datatype": "sc_lv", "bitwidth":2, "type": "signal", "bundle":{"name": "AXILiteS", "role": "RRESP" } },
{ "name": "s_axi_AXILiteS_BVALID", "direction": "out", "datatype": "sc_logic", "bitwidth":1, "type": "signal", "bundle":{"name": "AXILiteS", "role": "BVALID" } },
{ "name": "s_axi_AXILiteS_BREADY", "direction": "in", "datatype": "sc_logic", "bitwidth":1, "type": "signal", "bundle":{"name": "AXILiteS", "role": "BREADY" } },
{ "name": "s_axi_AXILiteS_BRESP", "direction": "out", "datatype": "sc_lv", "bitwidth":2, "type": "signal", "bundle":{"name": "AXILiteS", "role": "BRESP" } },
{ "name": "interrupt", "direction": "out", "datatype": "sc_logic", "bitwidth":1, "type": "signal", "bundle":{"name": "AXILiteS", "role": "interrupt" } },
{ "name": "ap_clk", "direction": "in", "datatype": "sc_logic", "bitwidth":1, "type": "clock", "bundle":{"name": "ap_clk", "role": "default" }} ,
{ "name": "ap_rst_n", "direction": "in", "datatype": "sc_logic", "bitwidth":1, "type": "reset", "bundle":{"name": "ap_rst_n", "role": "default" }} ]}
set ArgLastReadFirstWriteLatency {
game_of_life_step {
in_words_0 {Type I LastRead 0 FirstWrite -1}
in_words_1 {Type I LastRead 0 FirstWrite -1}
in_words_2 {Type I LastRead 0 FirstWrite -1}
in_words_3 {Type I LastRead 0 FirstWrite -1}
out_words_0 {Type O LastRead -1 FirstWrite 1}
out_words_1 {Type O LastRead -1 FirstWrite 1}
out_words_2 {Type O LastRead -1 FirstWrite 1}
out_words_3 {Type O LastRead -1 FirstWrite 1}}}
set hasDtUnsupportedChannel 0
set PerformanceInfo {[
{"Name" : "Latency", "Min" : "1", "Max" : "1"}
, {"Name" : "Interval", "Min" : "2", "Max" : "2"}
]}
set PipelineEnableSignalInfo {[
]}
set Spec2ImplPortList {
}
set maxi_interface_dict [dict create]
# RTL port scheduling information:
set fifoSchedulingInfoList {
}
# RTL bus port read request latency information:
set busReadReqLatencyList {
}
# RTL bus port write response latency information:
set busWriteResLatencyList {
}
# RTL array port load latency information:
set memoryLoadLatencyList {
}

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<profile>
<section name = "Vitis HLS Report for 'game_of_life_step'" level="0">
<item name = "Date">Tue Oct 20 17:51:19 2026
</item>
<item name = "Version">2025.1 (Build 6135595 on May 21 2025)</item>
<item name = "Project">game_of_life_practical3b</item>
<item name = "Solution">hls (Vivado IP Flow Target)</item>
<item name = "Product family">zynq</item>
<item name = "Target device">xc7z010-clg400-1</item>
</section>
<section name = "Performance Estimates" level="0">
<item name = "Timing">
<section name = "" level="1">
<item name = "Summary"><table name="" hasTotal="0">
<keys size="4">Clock, Target, Estimated, Uncertainty</keys>
<column name="ap_clk">10.00 ns, 6.928 ns, 2.70 ns</column>
</table>
</item>
</section>
</item>
<item name = "Latency">
<section name = "" level="1">
<item name = "Summary"><table name="" hasTotal="0">
<keys size="8">, min, max, min, max, min, max, Type</keys>
<column name="">1, 1, 10.000 ns, 10.000 ns, 2, 2, no</column>
</table>
</item>
<item name = "Detail">
<section name = "" level="1">
<item name = "Instance"><table name="" hasTotal="0">
<keys size="9">Instance, Module, min, max, min, max, min, max, Type</keys>
</table>
</item>
<item name = "Loop"><table name="" hasTotal="0">
<keys size="8">Loop Name, min, max, Latency, achieved, target, Count, Pipelined</keys>
</table>
</item>
</section>
</item>
</section>
</item>
</section>
</profile>

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<profile>
<section name = "Vitis HLS Report for 'game_of_life_step'" level="0">
<item name = "Date">Tue Oct 20 17:51:18 2026
</item>
<item name = "Version">2025.1 (Build 6135595 on May 21 2025)</item>
<item name = "Project">game_of_life_practical3b</item>
<item name = "Solution">hls (Vivado IP Flow Target)</item>
<item name = "Product family">zynq</item>
<item name = "Target device">xc7z010-clg400-1</item>
</section>
<section name = "Performance Estimates" level="0">
<item name = "Timing">
<section name = "" level="1">
<item name = "Summary"><table name="" hasTotal="0">
<keys size="4">Clock, Target, Estimated, Uncertainty</keys>
<column name="ap_clk">10.00 ns, 6.928 ns, 2.70 ns</column>
</table>
</item>
</section>
</item>
<item name = "Latency">
<section name = "" level="1">
<item name = "Summary"><table name="" hasTotal="0">
<keys size="8">, min, max, min, max, min, max, Type</keys>
<column name="">1, 1, 10.000 ns, 10.000 ns, 2, 2, no</column>
</table>
</item>
<item name = "Detail">
<section name = "" level="1">
<item name = "Instance"><table name="" hasTotal="0">
<keys size="9">Instance, Module, min, max, min, max, min, max, Type</keys>
</table>
</item>
<item name = "Loop"><table name="" hasTotal="0">
<keys size="8">Loop Name, min, max, Latency, achieved, target, Count, Pipelined</keys>
</table>
</item>
</section>
</item>
</section>
</item>
</section>
</profile>

66
Practicals/practical-3b/game_of_life_practical3b/game_of_life_practical3b/hls/.autopilot/db/game_of_life_step_dataflow_ana.wcfg Normal file
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<?xml version="1.0" encoding="UTF-8"?>
<wave_config>
<wave_state>
</wave_state>
<db_ref_list>
<db_ref path="game_of_life_step.wdb" id="1">
<top_modules>
<top_module name="apa_game_of_life_step_top" />
</top_modules>
</db_ref>
</db_ref_list>
<zoom_setting>
<ZoomStartTime time="0ns"></ZoomStartTime>
<ZoomEndTime time="2000ns"></ZoomEndTime>
<Cursor1Time time="0ns"></Cursor1Time>
</zoom_setting>
<column_width_setting>
<NameColumnWidth column_width="257"></NameColumnWidth>
<ValueColumnWidth column_width="84"></ValueColumnWidth>
</column_width_setting>
<WVObjectSize size="2" />
<wvobject type="group" fp_name="HLS Process Summary Group">
<obj_property name="label">HLS Process Summary</obj_property>
<obj_property name="DisplayName">label</obj_property>
<wvobject type="group" fp_name="/apatb_game_of_life_step_top/AESL_inst_game_of_life_step//AESL_inst_game_of_life_step_activity">
<obj_property name="label">AESL_inst_game_of_life_step_activity</obj_property>
<obj_property name="DisplayName">label</obj_property>
<obj_property name="UseFullPath">true</obj_property>
<obj_property name="ElementShortName">AESL_inst_game_of_life_step_activity</obj_property>
<obj_property name="ObjectShortName">AESL_inst_game_of_life_step_activity</obj_property>
<obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
<obj_property name="WaveformStyle">STYLE_ENUM_TRANSACTION</obj_property>
<obj_property name="EnumTransactionColorTable">0=blank ffff=blank 0bad=#FF0000</obj_property>
<obj_property name="UseCustomSignalColor">true</obj_property>
<obj_property name="CustomSignalColor">turquoise</obj_property>
<obj_property name="EnumTransactionValueTable">65535=blank</obj_property>
<obj_property name="Render_Data">/apatb_game_of_life_step_top/AESL_inst_game_of_life_step//AESL_inst_game_of_life_step_activity.dataflowTxWaveData.Cycles</obj_property>
<obj_property name="Value_Data">/apatb_game_of_life_step_top/AESL_inst_game_of_life_step//AESL_inst_game_of_life_step_activity.dataflowTxWaveData.OutStanding</obj_property>
<obj_property name="Detail_Data">/apatb_game_of_life_step_top/AESL_inst_game_of_life_step//AESL_inst_game_of_life_step_activity.dataflowTxTooltipData</obj_property>
</wvobject>
</wvobject>
<wvobject type="protoinst" fp_name="/apatb_game_of_life_step_top/AESL_inst_game_of_life_step//AESL_inst_game_of_life_step_activity">
<obj_property name="ElementShortName">AESL_inst_game_of_life_step_activity</obj_property>
<obj_property name="ObjectShortName">AESL_inst_game_of_life_step_activity</obj_property>
</wvobject>
<wvobject type="group" fp_name="AESL_inst_game_of_life_step_group">
<obj_property name="label">AESL_inst_game_of_life_step</obj_property>
<obj_property name="DisplayName">label</obj_property>
<wvobject type="group" fp_name="AESL_inst_game_of_life_step_Handshake_group">
<obj_property name="label">Block-level handshake</obj_property>
<obj_property name="DisplayName">label</obj_property>
<wvobject type="logic" fp_name="/apatb_game_of_life_step_top/AESL_inst_game_of_life_step/ap_start">
<obj_property name="ElementShortName">ap_start</obj_property>
<obj_property name="ObjectShortName">ap_start</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/apatb_game_of_life_step_top/AESL_inst_game_of_life_step/ap_ready">
<obj_property name="ElementShortName">ap_ready</obj_property>
<obj_property name="ObjectShortName">ap_ready</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/apatb_game_of_life_step_top/AESL_inst_game_of_life_step/ap_done">
<obj_property name="ElementShortName">ap_done</obj_property>
<obj_property name="ObjectShortName">ap_done</obj_property>
</wvobject>
</wvobject>
</wvobject>
</wave_config>

6
Practicals/practical-3b/game_of_life_practical3b/game_of_life_practical3b/hls/.autopilot/db/game_of_life_stepap_header.systemc.txt.ap_header.txt Normal file
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@@ -0,0 +1,6 @@
// ==============================================================
// Generated by Vitis HLS v2025.1
// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
// Copyright 2022-2025 Advanced Micro Devices, Inc. All Rights Reserved.
// ==============================================================

6
Practicals/practical-3b/game_of_life_practical3b/game_of_life_practical3b/hls/.autopilot/db/game_of_life_stepap_header.verilog.txt.ap_header.txt Normal file
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@@ -0,0 +1,6 @@
// ==============================================================
// Generated by Vitis HLS v2025.1
// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
// Copyright 2022-2025 Advanced Micro Devices, Inc. All Rights Reserved.
// ==============================================================

6
Practicals/practical-3b/game_of_life_practical3b/game_of_life_practical3b/hls/.autopilot/db/game_of_life_stepap_header.vhdl.txt.ap_header.txt Normal file
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@@ -0,0 +1,6 @@
-- ==============================================================
-- Generated by Vitis HLS v2025.1
-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
-- Copyright 2022-2025 Advanced Micro Devices, Inc. All Rights Reserved.
-- ==============================================================

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